Data Sheet S15843EJ3V0DS

11

8. RELATIONSHIP BETWEEN STB, POL AND OUTPUT WAVEFORM

When the STB is high level, all outputs became Hi-Z and the gray-scale voltage is output to the LCD in synchronization

with the falling edge of STB.

Therefore, high drive time of the output amplifier as below is determined by the CLK number of the required SRC pin

setting. Be sure to avoid using such as extremely changing the CLK frequency (ex. CLK stop).

Hi-Z

STB

Inside bias current

POL

Vx (odd output)

Vx (even output)

Hi-Z

Hi-Z

High drive time

High drive time

High drive time

9. SRC AND HIGH DRIVE TIME

The

SRC = H or open (high drive time: standard mode): High drive time (PWhp) of the output amplifier is in 64 CLK

period from falling edge of the STB.

SRC = L (high drive time: long-term mode): High drive time (PWhp) of the output amplifier is in 128 CLK period

from falling edge of the STB.

STB

CLK

Inside bias current

PWhp

We recommend a thorough simulation of the output amplifier in advance when set the SRC pin.