Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF HTML

LM4549A Datasheet(PDF) 20 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. LM4549A
Description  AC ’97 Rev 2.1 Codec with Sample Rate Conversion and National 3D Sound
Download  28 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
Logo 

LM4549A Datasheet(HTML) 20 Page - National Semiconductor (TI)

Zoom Inzoom in Zoom Outzoom out
 20 / 28 page
background image
AC Link Serial Interface Protocol
(Continued)
SLOT 0, INPUT FRAME
Bit
Description
Comment
15
Codec Ready
Bit
1 = AC Link Interface Ready
14
Slot 1 data
valid
1 = Valid Status Address or
Slot Request
13
Slot 2 data
valid
1 = Valid Status Data
12
Slot 3 data
valid
1 = Valid PCM Data
(Left ADC)
11
Slot 4 data
valid
1 = Valid PCM Data
(Right ADC)
SDATA_IN: Slot 1 – Status Address / Slot Request Bits
This slot echoes (in bits 18 – 12) the 7-bit address of the
codec control/status register received from the controller as
part of a read-request in the previous frame. If no read-
request was received, the codec stuffs these bits with zeros.
Bits 11, 10 are Slot Request bits that support the Variable
Rate Audio (VRA) capabilities of the LM4549A. For all codec
Primary and Secondary modes, the left and right channels of
the DAC take PCM data from slots 3 and 4 in the Output
Frame respectively. The codec uses bits 11 and 10 to re-
quest DAC data from these two slots. If bits 11 and 10 are set
to 0, the controller should respond with valid PCM data in
slots 3 and 4 of the next Output Frame. If bits 11 and 10 are
set to 1, the controller should not send data.
The codec has full control of the slot request bits. By default,
data is requested in every frame, corresponding to a sample
rate equal to the frame rate (SYNC frequency) – 48 kHz
when XTAL_IN = 24.576 MHz. To send samples at a rate
below the frame rate, a controller should set VRA = 1 (bit 0
in the Extended Audio Control/Status register, 2Ah) and
program the desired rate into the PCM DAC Rate register,
2Ch. Both DAC channels operate at the same sample rate.
Values for common sample rates are given in the Register
Description section (Sample Rate Control Registers, 2Ch,
32h) but any rate between 4 kHz and 48 kHz (to a resolution
of 1 Hz) is supported. Slot Requests from the LM4549A are
issued completely deterministically. For example if a sample
rate of 8000 Hz is programmed into 2Ch then the LM4549A
will always issue a slot request in every sixth frame. A
frequency of 9600 Hz will result in a request every fifth frame
while a frequency of 8800 Hz will cause slot requests to be
spaced alternately five and six frames apart. This determin-
ism makes it easy to plan task scheduling on a system
controller and simplifies application software development.
The LM4549A will ignore data in Output Frame slots that do
not follow an Input Frame with a Slot Request. For example,
if the LM4549A is expecting data at a 8000 Hz rate yet the
AC ’97 Digital Audio Controller continues to send data at
48000 Hz, then only those one-in-six audio samples that
follow a Slot Request will be used by the DAC. The rest will
be discarded.
Bits 9 – 2 are request bits for slots not used by the LM4549A
and are stuffed with zeros. Bits 1 and 0 are reserved and are
also stuffed with zeros.
SLOT 1, INPUT FRAME
Bits
Description
Comment
19
Reserved
Stuffed with "0" by LM4549A
18:12
Status Register
Index
Echo of the requested Status
Register address.
11
Slot 3 Request
bit
(For left DAC
PCM data)
0 = Controller should send
valid data in Slot 3 of the
next Output Frame.
1 = Controller should not
send Slot 3 data.
10
Slot 4 Request
bit
(For right DAC
PCM data)
0 = Controller should send
valid data in Slot 4 of the
next Output Frame.
1 = Controller should not
send Slot 4 data.
9:2
Unused Slot
Request bits
Stuffed with "0"s by LM4549A
1,0
Reserved
Stuffed with "0"s by LM4549A
SDATA_IN: Slot 2 – Status Data
This slot returns 16-bit status data read from a codec control/
status register. The codec sends the data in the frame fol-
lowing a read-request by the controller (bit 15, slot 1 of the
Output Frame). If no read-request was made in the previous
frame the codec will stuff this slot with zeros.
SLOT 2, INPUT FRAME
Bits
Description
Comment
19:4
Status Data
Data read from a codec
control/status register.
Stuffed with “0”s if no
read-request in previous frame.
3:0
Reserved
Stuffed with "0"s by LM4549A
SDATA_IN: Slot 3 – PCM Record Left Channel
This slot contains sampled data from the left channel of the
stereo ADC. The signal to be digitized is selected using the
Record Select register (1Ah) and subsequently routed
through the Record Select Mux and the Record Gain ampli-
fier to the ADC.
This is a 20-bit slot and the digitized 18-bit PCM data is
transmitted in an MSB justified format. The remaining 2
LSBs are stuffed with zeros.
SLOT 3, INPUT FRAME
Bits
Description
Comment
19:2
PCM Record
Left Channel
data
18-bit PCM sample from left
ADC
1:0
Reserved
Stuffed with "0"s by LM4549A
www.national.com
20


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn