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CY28346-2
Document #: 38-07509 Rev. *A
Page 8 of 20
PD# Deassertion
The power-up latency between PD# rising to a valid logic ‘1’
level and the starting of all clocks is less than 3.0 ms.
P C I 33M H z
PW R D W N #
CP UT 1 3 3 M H z
C P U C 133M H z
R E F 14.318 M H z
US B 4 8 M H z
S D R A M 133 M H z
DD RT 1 3 3 M H z
DD RC 1 3 3 M H z
AG P 6 6 M H z
Figure 2. Power-down Assertion Timing Waveforms–Unbuffered Mode
CPU 133MHz
3V66
CPU# 133MHz
REF 14.318MHz
USB 48MHz
PCIF / APIC
33MHz
66In
66Buff
PWRDWN#
66Buff1 / GMCH
400uS max
<1.8mS
PCI 33MHz
30uS min
Figure 3. Power-down Deassertion Timing Waveforms
Table 5. PD# Functionality
PD#
DRCG
66CLK (0:2)
PCIF/PCI
PCI
USB/DOT
1
66M
66Input
66Input/2
66Input/2
48M
0
Low
Low
Low
Low
Low
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