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CY28346-2 Datasheet(PDF) 3 Page - Cypress Semiconductor

Part No. CY28346-2
Description  Clock Synthesizer with Differential CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28346-2 Datasheet(HTML) 3 Page - Cypress Semiconductor

 
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CY28346-2
Document #: 38-07509 Rev. *A
Page 3 of 20
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts block write and block
read operations from the controller. For block write/read
operation, the bytes must be accessed in sequential order
from lowest to highest byte (most significant bit first) with the
ability to stop after any complete byte has been transferred.
The block write and block read protocol is outlined in Table 2.
The slave receiver address is 11010010 (D2h).
41
VSSIREF
PWR Current reference programming input for CPU buffers. A resistor is
connected between this pin and IREF. This pin should also be returned
to device VSS.
26
VDDA
PWR Analog power input. Used for PLL and internal analog circuits. It is also
specifically used to detect and determine when power is at an acceptable
level to enable the device to operate.
Pin Description (continued)
Pin
Name
PWR
I/O
Description
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1
Start
1
Start
2:8
Slave address – 7 bits
2:8
Slave address – 7 bits
9
Write = 0
9
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bit
‘00000000’ stands for block operation
11:18
Command Code – 8 bit
‘00000000’ stands for block operation
19
Acknowledge from slave
19
Acknowledge from slave
20:27
Byte Count – 8 bits
20
Repeat start
28
Acknowledge from slave
21:27
Slave address – 7 bits
29:36
Data byte 1 – 8 bits
28
Read = 1
37
Acknowledge from slave
29
Acknowledge from slave
38:45
Data byte 2 – 8 bits
30:37
Byte count from slave – 8 bits
46
Acknowledge from slave
38
Acknowledge
....
......................
39:46
Data byte from slave – 8 bits
....
Data Byte (N–1) –8 bits
47
Acknowledge
....
Acknowledge from slave
48:55
Data byte from slave – 8 bits
....
Data Byte N –8 bits
56
Acknowledge
....
Acknowledge from slave
....
Data bytes from slave/Acknowledge
....
Stop
....
Data byte N from slave – 8 bits
....
Not Acknowledge
....
Stop


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