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CY28346-2 Datasheet(PDF) 2 Page - Cypress Semiconductor

Part No. CY28346-2
Description  Clock Synthesizer with Differential CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28346-2 Datasheet(HTML) 2 Page - Cypress Semiconductor

 
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CY28346-2
Document #: 38-07509 Rev. *A
Page 2 of 20
Pin Description
Pin
Name
PWR
I/O
Description
2XIN
VDD
I
Oscillator Buffer Input. Connect to a crystal or to an external clock.
3XOUT
VDD
O
Oscillator Buffer Output. Connect to a crystal. Do not connect when an
external clock is applied at XIN.
52, 51, 49, 48,
45, 44
CPUT(0:2),
CPUC(0:2)
VDD
O
Differential host output clock pairs. See Table 1 for frequencies and
functionality.
10, 11, 12, 13,
16, 17, 18
PCI(0:6)
VDDP
O
PCI clock outputs. Are synchronous to 66IN or 3V66 clock. See Table 1.
5, 6, 7
PCIF (0:2)
VDD
O
33-MHz PCI clocks, which are
÷2 copies of 66IN or 3V66 clocks, may
be free running (not stopped when PCI_STP# is asserted LOW) or
may be stoppable depending on the programming of SMBus
register Byte3, Bits (3:5).
56
REF
VDD
O
Buffered output copy of the device’s XIN clock.
42
IREF
VDD
I
Current reference programming input for CPU buffers. A resistor is
connected between this pin and VSSIREF.
28
VTT_PWRGD#
VDD
I
Qualifying input that latches S(0:2) and MULT0. When this input is at
a logic low, the S(0:2) and MULT0 are latched.
39
48M_USB
VDD48
O
Fixed 48-MHz USB clock outputs.
38
48M_DOT
VDD48
O
Fixed 48-MHZ DOT clock outputs.
33
3V66_0
VDD
O
3.3V 66-MHz fixed frequency clock.
35
3V66_1/VCH
VDD
O
3.3V clock selectable with SMBus byte0, Bit5, when Byte5, Bit5.
When Byte 0 Bit 5 is at a logic 1, then this pin is a 48M output clock. When
byte0, Bit5 is a logic 0, then this is a 66M output clock (default).
25
PD#
VDD
I
PU
This pin is a power-down mode pin. A logic LOW level causes the
device to enter a power-down state. All internal logic is turned off except
for the SMBus logic. All output buffers are stopped.
43
MULT0
VDD
I
PU
Programming input selection for CPU clock current multiplier.
55, 54
S(0,1)
I
I
Frequency select inputs. See Table 1
29
SDATA
I
I
Serial data input. Conforms to the SMBus specification of a Slave
Receive/Transmit device. It is an input when receiving data. It is an open
drain output when acknowledging or transmitting data.
30
SCLK
I
I
Serial clock input. Conforms to the SMBus specification.
40
S2
VDD
I
T
Frequency select input. See Table 1. This is a Tri-level input that is
driven HIGH, LOW, or driven to a intermediate level.
34
PCI_STP#
VDD
I
PU
PCI clock disable input. When asserted LOW, PCI (0:6) clocks are
synchronously disabled in a LOW state. This pin does not effect PCIF
(0:2) clocks’ outputs if they are programmed to be PCIF clocks via the
device’s SMBus interface.
53
CPU_STP#
VDD
I
PU
CPU clock disable input. When asserted LOW, CPUT (0:2) clocks are
synchronously disabled in a HIGH state and CPUC(0:2) clocks are
synchronously disabled in a LOW state.
24
66IN/3V66_5
VDD
I/O
Input connection for 66CLK(0:2) output clock buffers if S2 = 1, or
output clock for fixed 66-MHz clock if S2 = 0. See Table 1.
21, 22, 23
66B(0:2)/
3V66(2:4)
VDD
O
3.3V clock outputs. These clocks are buffered copies of the 66IN clock
or fixed at 66 MHz. See Table 1.
1, 8, 14, 19, 32,
37, 46, 50
VDD
PWR 3.3V power supply.
4, 9, 15, 20, 27,
31, 36, 47
VSS
PWR Common ground.


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