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CY28346-2 Datasheet(PDF) 17 Page - Cypress Semiconductor

Part No. CY28346-2
Description  Clock Synthesizer with Differential CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28346-2 Datasheet(HTML) 17 Page - Cypress Semiconductor

 
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CY28346-2
Document #: 38-07509 Rev. *A
Page 17 of 20
Test and Measurement Set-up
For Differential CPU Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
Notes:
23. CPU_STP# and PCI _STP# setup time with respect to any PCIF clock to guarantee that the effected clock will stop or start at the next PCIF clock’s rising edge.
24. When Crystal meets minimum 40-ohm device series resistance specification.
Tr / Tf
REF Rise and Fall
Times
1.0
4.0
1.0
4.0
1.0
4.0
1.0
4.0
ns
8, 21
Tccj
REF Cycle to
Cycle Jitter
1000
1000
1000
1000
ps
8, 9
Tpzl/Tpzh
Output Enable
Delay (all outputs)
1.0
10.0
1.0
10.0
1.0
10.0
1.0
10.0
ns
6
Tplz/Tpzh
Output disable
delay (all outputs)
1.0
10.0
1.0
10.0
1.0
10.0
1.0
10.0
ns
6
Tstable
All Clock Stabili-
zation from
Power-up
33
33
ms
6
Tss
Stopclock Set-up
Time
10.0
10.0
10.0
10.0
ns
23
Tsh
Stopclock Hold
Time
00
0
0
ns
23
Tsu
Oscillator Start-up
Time
1.2
1.2
1.2
1.2
ms
24
AC Parameters (VDD = VDDA = 3.3V ±5%) (continued)
Parameter
Description
66 MHz
100 MHz
133 MHz
200 MHz
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
M ea surem ent P o in t
2p F
CP U T
M U LT SEL
T
PC B
T
PC B
CP U C
220Ω
63.4Ω
63.4Ω
475Ω
33.2Ω
33.2Ω
M e asu rem en t P oint
2pF
Figure 15. 1.0V Test Load Termination


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