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CY28346-2 Datasheet(PDF) 15 Page - Cypress Semiconductor

Part No. CY28346-2
Description  Clock Synthesizer with Differential CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28346-2 Datasheet(HTML) 15 Page - Cypress Semiconductor

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CY28346-2
Document #: 38-07509 Rev. *A
Page 15 of 20
Tccj
CPU Cycle to
Cycle Jitter
150
150
150
150
ps
11, 12, 13
Tr/Tf
CPUT and CPUC
Rise and Fall
Times
175
700
175
700
175
700
175
700
ps
11, 14, 16
Rise/Fall Matching
20%
20%
20%
20%
14, 15, 13
DeltaTr
Rise Time
Variation
125
125
125
125
ps
14, 13
DeltaTf
Fall Time
Variation
125
125
125
125
ps
14, 13
Vcross
Crossing Point
Voltage at 0.7V
Swing
280
430
280
430
280
430
280
430
mV
11, 13
CPU at 1.0V Timing
Tdc
CPUT and CPUC
Duty Cycle
45
55
45
55
45
55
45
55
%
11, 12
Tperiod
CPUT and CPUC
Period
14.85
15.3
9.85
10.2
7.35
7.65
4.85
5.1
nS
11, 12
Tskew
Any CPU to Any
CPU Clock Skew
100
100
100
100
pS
8, 11, 12
Tccj
CPU Cycle to
Cycle Jitter
150
150
150
150
pS
8, 12
Differential
Tr/Tf
CPUT and CPUC
Rise and Fall Times
175
467
175
467
175
467
175
467
ps
11, 16
SE-
DeltaSlew
Absolute Single-
ended Rise/Fall
Waveform
Symmetry
325
325
325
325
ps
17, 18
Vcross
Cross Point at
1.0V swing
510
760
510
760
510
760
510
760
mV
18
3V66
Tdc
3V66 Duty Cycle
45
554555
45
5545
55
%
8, 9
Tperiod
3V66 Period
15.0
15.3
15.0
15.3
15.0
15.3
15.0
15.3
ns
5, 8, 9
Thigh
3V66 High Time
4.95
4.95
4.95
4.95
ns
19
Tlow
3V66 Low Time
4.55
4.55
4.55
4.55
ns
20
Tr / Tf
3V66 Rise and
Fall Times
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
ns
21
Tskew
Unbuffered
3V66 to 3V66
Clock Skew
500
500
500
500
ps
8, 9
Tskew
Buffered
3V66 to 3V66
Clock Skew
250
250
250
250
ps
8, 9
Tccj
DRCG Cycle to
Cycle Jitter
250
250
250
250
ps
8, 9
14. Measured from Vol = 0.175V to Voh = 0.525V.
15. Determined as a fraction of 2*(Trise – Tfall)/ (Trise + Tfall).
16. Measurement taken from differential waveform, from –0.35V to +0.35V.
17. Measurements taken from common mode waveforms, measure rise/fall time from 0.41 to 0.86V. Rise/fall time matching is defined as “the instantaneous
difference between maximum clk rise (fall) and minimum clk# fall (rise) time or minimum clk rise (fall) and maximum clk# fall (rise) time”. This parameter is
designed form waveform symmetry.
18. Measured in absolute voltage, i.e. single-ended measurement.
19. THIGH is measured at 2.4V for non host outputs.
20. TLOW is measured at 0.4V for all outputs.
21. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals (see test and measurement set-up section of this data
sheet).
AC Parameters (VDD = VDDA = 3.3V ±5%) (continued)
Parameter
Description
66 MHz
100 MHz
133 MHz
200 MHz
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.


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