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CY28346-2 Datasheet(PDF) 14 Page - Cypress Semiconductor

Part No. CY28346-2
Description  Clock Synthesizer with Differential CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28346-2 Datasheet(HTML) 14 Page - Cypress Semiconductor

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CY28346-2
Document #: 38-07509 Rev. *A
Page 14 of 20
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VDD
Core Supply Voltage
–0.5
4.6
V
VDD_A
Analog Supply Voltage
–0.5
4.6
V
VIN
Input Voltage
Relative to V SS
–0.5
VDD + 0.5
VDC
TS
Temperature, Storage
Non-functional
–65
150
°C
TA
Temperature, Operating Ambient
Functional
0
85
°C
TJ
Temperature, Junction
Functional
150
°C
ØJC
Dissipation, Junction to Case
Mil-Spec 883E Method 1012.1
45
°C/W
ØJA
Dissipation, Junction to Ambient
JEDEC (JESD 51)
15
°C/W
ESDHBM
ESD Protection (Human Body Model)
MIL-STD-883, Method 3015
2000
V
Ul-94
Flammability Rating
V–0 @1/8 in.
10
ppm
MSL
Moisture Sensitivity Level
1
DC Parameters (VDD = VDDA = 3.3V ±5%)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Idd3.3V
Dynamic Supply Current
All frequencies at maximum values[3]
280
mA
Ipd3.3V
Power-down Supply Current
PD# Asserted
Note 4
mA
Cin
Input Pin Capacitance
5pF
Cout
Output Pin Capacitance
6pF
Lpin
Pin Inductance
7nH
Cxtal
Crystal Pin Capacitance
Measured from the Xin or Xout Pin to Ground.
30
36
42
pF
AC Parameters (VDD = VDDA = 3.3V ±5%)
Parameter
Description
66 MHz
100 MHz
133 MHz
200 MHz
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Crystal
Tdc
Xin Duty Cycle
47.5
52.5
47.5
52.5
47.5
52.5
47.5
52.5
%
5, 6, 7
Tperiod
Xin Period
69.84
71.0
69.84
71.0
69.84
71.0
69.84
71.0
ns
5, 8, 9, 6
Vhigh
Xin High Voltage
0.7Vdd
Vdd
0.7Vdd
Vdd
0.7Vdd
Vdd
0.7Vdd
Vdd
V
Vlow
Xin Low Voltage
0
0.3Vdd
0
0.3Vdd
0
0.3Vdd
0
0.3Vdd
V
Tr/Tf
Xin Rise and Fall
Times
10.0
10.0
10.0
10.0
ns
10
Tccj
Xin Cycle to Cycle
Jitter
500
500
500
500
ps
8, 11, 6
CPU at 0.7V Timing
Tdc
CPUT and CPUC
Duty Cycle
45
55
45
55
45
55
45
55
%
11, 12, 13
Tperiod
CPUT and CPUC
Period
14.85
15.3
9.85
10.2
7.35
7.65
4.85
5.1
ns
11, 12, 13
Tskew
Any CPU to CPU
Clock Skew
100
100
100
100
ps
8, 11, 12
Notes:
3.
All outputs loaded as per maximum capacitive load table.
4.
Absolute value = ((Programmed CPU Iref) x (2)) + 10 mA.
5.
This parameter is measured as an average over 1-
µs duration, with a crystal center frequency of 14.31818 MHz
6.
When Xin is driven from an external clock source.
7.
This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock
duty cycle will not be within data sheet specifications.
8.
All outputs loaded as perTable 10 below.
9.
Probes are placed on the pins and measurements are acquired at 1.5V for 3.3V signals (see test and measurement set-up section of this data sheet).
10. Measured between 0.2Vdd and 0.7Vdd.
11. This measurement is applicable with Spread ON or Spread OFF.
12. Measured at crossing point (Vx) or where subtraction of CLK-CLK# crosses 0 volts Measured from Vol = 0.175V to Voh = 0.525V.
13. Test load is Rta = 33.2 ohms, Rd = 49.9 ohms.


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