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CY28346-2 Datasheet(PDF) 11 Page - Cypress Semiconductor

Part No. CY28346-2
Description  Clock Synthesizer with Differential CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28346-2 Datasheet(HTML) 11 Page - Cypress Semiconductor

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CY28346-2
Document #: 38-07509 Rev. *A
Page 11 of 20
PC I_STP #
PC IF
PC I
setup
t
Figure 7. PCI_STP# Deassertion Waveforms
Figure 8. VTT_PWRGD# Timing Diagram
VID
SEL
VTT_PWRGD#
PWRGD
VDD Clock Gen
Clock State
Clock Outputs
Clock VCO
0.2-0.3mS
Delay
State 0
State 2
State 3
Wait for
VTT_PWRGD#
Sample Sels
Off
Off
On
On
State 1
Device is not affected,
VTT_PWRGD# is ignored.
VTT_PWRGD# = Low
Delay
>0.25mS
S1
Power Off
S0
VDDA = 2.0V
Sample
Inputs straps
S2
Normal
Operation
Wait for <1.8ms
Enable Outputs
S3
VTT_PWRGD# = toggle
VDD3.3= off
Figure 9. Clock Generator Power-up/Run State Program
Table 7. Host Clock (HCSL) Buffer Characteristics
Characteristic
Minimum
Maximum
Ro
3000 Ohms (recommended)
N/A
Ros
Vout
N/A
1.2V


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