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CY28346-2 Datasheet(PDF) 6 Page - Cypress Semiconductor

Part No. CY28346-2
Description  Clock Synthesizer with Differential CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28346-2 Datasheet(HTML) 6 Page - Cypress Semiconductor

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CY28346-2
Document #: 38-07509 Rev. *A
Page 6 of 20
Dial-a-Frequency Feature
SMBus Dial-a-Frequency feature is available in this device via
Byte8 and Byte9. See our App Note AN-0025 for details on our
Dial-a-Frequency feature.
P is a large value PLL constant that depends on the frequency
selection achieved through the hardware selectors (S1, S0).
P value may be determined from Table 3.
Dial-a-dB Features
SMBus Dial-a-dB feature is available in this device via Byte8
and Byte9.
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique used to
minimizing EMI radiation generated by repetitive digital
signals. A clock presents the greatest EMI energy at the center
frequency it is generating. Spread Spectrum distributes this
energy over a specific and controlled frequency bandwidth
therefore causing the average energy at any one point in this
band to decrease in value. This technique is achieved by
modulating the clock away from its resting frequency by a
certain percentage (which also determines the amount of EMI
reduction). In this device, Spread Spectrum is enabled by
setting specific register bits in the SMBus control Bytes.
Table 4 is a listing of the modes and percentages of Spread
Spectrum modulation that this device incorporates.
Byte 7: Watchdog Time Stamp Register
Bit
@Pup
Name
Description
70
Reserved
60
Reserved
50
Reserved
40
Reserved
30
Reserved
20
Reserved
10
Reserved
00
Reserved
Byte 8: Dial-a-Frequency Control Register N (all bits are read and write functional)
Bit
@Pup
Name
Description
70
N7, MSB
60
N6
50
N5
40
N4
30
N3
20
N2
10
N3
00
N0, LSB
Byte 9: Dial-a-Frequency Control Register R (all bits are read and write functional)
Bit
@Pup
Name
Description
70
R6 MSB
60
R5
50
R4
40
R3
30
R2
20
R1
10
R0, LSB
0
0
R and N register load gate 0 = gate closed (data is latched), 1 = gate open
(data is loading from SMBus registers into R and N)
Table 3. P Value
S(1:0)
P
0 0
32005333
0 1
48008000
1 0
96016000
1 1
64010667


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