SMJ44C251B

262144 BY 4-BIT

MULTIPORT VIDEO RAM

SGMS058A – MARCH 1995 – REVISED JUNE 1995

21

POST OFFICE BOX 1443

timing requirements over recommended ranges of supply voltage and operating free-air

ALT.

’44C251B - 10

’44C251B - 12

UNIT

SYMBOL

MIN

MAX

MIN

MAX

UNIT

tc(rd)

Cycle time, read (see Note 9)

tRC

190

220

ns

tc( W )

Cycle time, write (see Note 9)

tWC

190

220

ns

tc(rdW)

Cycle time, read-modify-write (see Note 9)

tRMW

250

290

ns

tc(P)

Cycle time, page-mode read or write (see Note 9)

tPC

60

70

ns

tc(rdWP)

Cycle time, page-mode read-modify-write (see Note 9)

tPRMW

105

125

ns

tc( TRD)

Cycle time, read transfer (see Note 9)

tRC

190

220

ns

tc( TW )

Cycle time, write transfer (see Note 9)

tWC

190

220

ns

tc(SC)

Cycle time, serial clock (see Notes 9 and 10)

tSCC

30

35

ns

tw(CH)

Pulse duration, CAS high

tCPN

20

30

ns

tw(CL)

Pulse duration, CAS low (see Note 11)

tCAS

25

75 000

30

75 000

ns

tw(RH)

Pulse duration, RAS high

tRP

80

90

ns

tw(RL)

Pulse duration, RAS low (see Note 12)

tRAS

100

75 000

120

75 000

ns

tw( WL)

Pulse duration, W low

tWP

25

25

ns

tw( TRG)

Pulse duration, TRG low

25

30

ns

tw(SCH)

Pulse duration, SC high

tSC

10

12

ns

tw(SCL)

Pulse duration, SC low

tSCP

10

12

ns

tw(SEL)

Pulse duration, SE low

tSE

35

40

ns

tw(SEH)

Pulse duration, SE high

tSEP

35

40

ns

tw(GH)

Pulse duration, TRG high

tTP

30

30

ns

tw(RL)P

Pulse duration, RAS low (page mode)

100

75 000

120

75 000

ns

tsu(CA)

Setup time, column address

tASC

0

0

ns

tsu(SFC)

Setup time, DSF before CAS low

tFSC

0

0

ns

tsu(RA)

Setup time, row address

tASR

0

0

ns

tsu( WMR)

Setup time, W before RAS low

tWSR

0

0

ns

tsu(DQR)

Setup time, DQ before RAS low

tMS

0

0

ns

tsu( TRG)

Setup time, TRG before RAS low

tTHS

0

0

ns

tsu(SE)

Setup time, SE before RAS low (see Note 13)

tESR

0

0

ns

tsu(SESC)

Setup time, serial write disable

tSWIS

10

15

ns

tsu(SFR)

Setup time, DSF before RAS low

tFSR

0

0

ns

tsu(DCL)

Setup time, data before CAS low

tDSC

0

0

ns

tsu(DWL)

Setup time, data before W low

tDSW

0

0

ns

tsu(rd)

Setup time, read command

tRCS

0

0

ns

tsu( WCL)

Setup time, early write command before CAS low

tWCS

0

0

ns

† Timing measurements are referenced to VIL max and VIH min.

NOTES:

9. All cycle times assume tt = 5 ns.

10. When the odd tap is used (tap address can be 0 – 511, and odd taps are 1, 3, 5, etc.), the cycle time for SC in the first serial data

out cycle needs to be 70 ns minimum.

11. In a read-modify-write cycle, td(CLWL) and tsu( WCH) must be observed. Depending on the user’s transition times, this may require

additional CAS low time [tw(CL)].

12. In a read-modify-write cycle, td(RLWL) and tsu( WRH) must be observed. Depending on the user’s transition times, this may require

additional RAS low time [tw(RL)].

13. Register-to-memory (write) transfer cycles only