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MST703-LF Datasheet(PDF) 12 Page - List of Unclassifed Manufacturers

Part # MST703-LF
Description  Small Size LCD TV Processor with Video Decoder
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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MST703-LF Datasheet(HTML) 12 Page - List of Unclassifed Manufacturers

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Mstar Confidential
for 深圳市江启科技有限公司
Internal Use Only
MST703
Small Size LCD TV Processor with Video Decoder
Preliminary Data Sheet Version 0.1
- 12 -
11/24/2010
Copyright © 2010 MStar Semiconductor, Inc. All rights reserved.
Scaler Register (Bank = 00, Registers 01h ~ 9Fh)
Scaler Register (Bank=00, Registers 01h ~ 9Fh)
Index
Name
Bits
Description
DBFC
7:0
Default : 0x80
Access : R/W
-
7:3
Reserved.
DBL[1:0]
2:1
Double Buffer Load.
00: Keep old register value.
01: Load new data (auto reset to 00 when load finish).
10: Automatically load data at VSYNC blanking.
11: Reserved.
01h
DB_EN
0
Double Buffer Enable.
0: Disable.
1: Enable.
ISELECT
7:0
Default : 0x00
Access : R/W
NIS
7
No Input Source.
0: Input source active.
1: Input source inactive, output is free-run.
STYPE[1:0]
6:5
Input Sync Type.
00: Auto detected.
01: Input is separated HSYNC and VSYNC.
10: Input is Composite sync.
11: Input is sync-on-green (SOG).
COMP
4
CSYNC/SOG select (only useful when STYPE = 00).
0: CSYNC.
1: SOG.
ICS
3
Input Color Space.
0: RGB.
1: YCbCr.
IHSU
2
Input Sync Usage.
When EXTVD=0:
0: Use HSYNC to perform mode detection, HSOUT from ADC to
sample pixel.
1: Use HSYNC only.
When EXTVD=1:
0: Normal.
1: Output black at blanking.
BYPASSMD
1
By-Pass Mode for interlace-input-interlace-output.
02h
EXTVD
0
0: Select analog input (CVBS/S-Video/RGB/YCbCr).
1: Select digital input (CCIR656).
03h
IPCTRL2
7:0
Default : 0x18
Access : R/W
Free Datasheet http://www.datasheet4u.net/


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