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EP1C12F100I7 Datasheet(PDF) 34 Page - Altera Corporation

Part # EP1C12F100I7
Description  Cyclone FPGA Family
Download  94 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1C12F100I7 Datasheet(HTML) 34 Page - Altera Corporation

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Altera Corporation
Cyclone FPGA Family Data Sheet
Preliminary Information
Figure 21. Single-Port Mode
Global Clock
Network &
Phase-Locked
Loops
Cyclone devices provide a global clock network and up to two PLLs for a
complete clock management solution.
Global Clock Network
There are four dedicated clock pins (CLK[3..0], two pins on the left side
and two pins on the right side) that drive the global clock network, as
shown in Figure 22. PLL outputs, logic array, and dual-purpose clock
(DPCLK[7..0]) pins can also drive the global clock network.
The eight global clock lines in the global clock network drive throughout
the entire device. The global clock network can provide clocks for all
resources within the device
IOEs, LEs, and memory blocks. The global
clock lines can also be used for control signals, such as clock enables and
synchronous or asynchronous clears fed from the external pin, or DQS
signals for DDR SDRAM or FCRAM interfaces. Internal logic can also
drive the global clock network for internally generated global clocks and
asynchronous clears, clock enables, or other control signals with large
fanout. Figure 22 shows the various sources that drive the global clock
network.
6
D
ENA
Q
D
ENA
Q
D
ENA
Q
D
ENA
Q
data[ ]
address[ ]
RAM/ROM
256
× 16
512
× 8
1,024
× 4
2,048
× 2
4,096
× 1
Data In
Address
Write Enable
Data Out
outclken
inclken
inclock
outclock
Write
Pulse
Generator
wren
6 LAB Row
Clocks
To MultiTrack
Interconnect


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