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EP1C12F100I7 Datasheet(PDF) 93 Page - Altera Corporation

Part # EP1C12F100I7
Description  Cyclone FPGA Family
Download  94 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1C12F100I7 Datasheet(HTML) 93 Page - Altera Corporation

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Altera Corporation
93
Preliminary Information
Cyclone FPGA Family Data Sheet
Note to Tables 69
− 70:
(1)
EP1C3 devices do not support the PCI I/O standard. These parameters are only
available on row I/O pins.
Software
Cyclone devices are supported by the Altera Quartus II design software,
which provides a comprehensive environment for system-on-a-
programmable-chip (SOPC) design. The Quartus II software includes
HDL and schematic design entry, compilation and logic synthesis, full
simulation and advanced timing analysis, SignalTap II logic analysis, and
device configuration. See the Design Software Selector Guide for more
details on the Quartus II software features.
The Quartus II software supports the Windows 2000/NT/98, Sun Solaris,
Linux Red Hat v7.1 and HP-UX operating systems. It also supports
seamless integration with industry-leading EDA tools through the
NativeLink® interface.
Device Pin-
Outs
Device pin-outs for Cyclone devices are available on the Altera web site
(http://www.altera.com).
Ordering
Information
Figure 39 describes the ordering codes for Cyclone devices. For more
information on a specific package, refer to the Altera Device Package
Information Data Sheet.
Table 70. Cyclone Maximum Output Clock Rate for Row Pins
I/O Standard
-6 Speed
Grade
-7 Speed
Grade
-8 Speed
Grade
Unit
LVTTL
304
304
304
MHz
2.5 V
220
220
220
MHz
1.8 V
213
213
213
MHz
1.5 V
166
166
166
MHz
LVCMOS
304
304
304
MHz
SSTL-3 class I
100
100
100
MHz
SSTL-3 class II
100
100
100
MHz
SSTL-2 class I
134
134
134
MHz
SSTL-2 class II
134
134
134
MHz
3.3-V PCI (1)
66
66
66
MHz
LVDS
231
231
231
MHz


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