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EP1C12F100I7 Datasheet(PDF) 48 Page - Altera Corporation

Part # EP1C12F100I7
Description  Cyclone FPGA Family
Download  94 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1C12F100I7 Datasheet(HTML) 48 Page - Altera Corporation

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Altera Corporation
Cyclone FPGA Family Data Sheet
Preliminary Information
The pin’s datain signals can drive the logic array. The logic array drives
the control and data signals, providing a flexible routing resource. The
row or column IOE clocks, io_clk[5..0], provide a dedicated routing
resource for low-skew, high-speed clocks. The global clock network
generates the IOE clocks that feed the row or column I/O regions (see
“Global Clock Network & Phase-Locked Loops” on page 34). Figure 30
illustrates the signal paths through the I/O block.
Figure 30. Signal Path through the I/O Block
Each IOE contains its own control signal selection for the following
control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset,
clk_in
, and clk_out. Figure 31 illustrates the control signal selection.
Row or Column
io_clk[5..0]
io_datain
comb_io_datain
io_dataout
io_coe
oe
ce_in
ce_out
io_cce_in
aclr/preset
io_cce_out
sclr
io_caclr
clk_in
io_cclk
clk_out
dataout
Data and
Control
Signal
Selection
IOE
To Logic
Array
From Logic
Array
To Other
IOEs
io_csclr


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