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EP1C12F100I7 Datasheet(PDF) 47 Page - Altera Corporation

Part # EP1C12F100I7
Description  Cyclone FPGA Family
Download  94 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1C12F100I7 Datasheet(HTML) 47 Page - Altera Corporation

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Altera Corporation
47
Preliminary Information
Cyclone FPGA Family Data Sheet
Figure 29. Column I/O Block Connection to the Interconnect
Notes to Figure 29:
(1)
The 21 data and control signals consist of three data out lines, io_dataout[2..0], three output enables,
io_coe[2..0]
, three input clock enables, io_cce_in[2..0], three output clock enables, io_cce_out[2..0],
three clocks, io_cclk[2..0], three asynchronous clear signals, io_caclr[2..0], and three synchronous clear
signals, io_csclr[2..0].
(2)
Each of the three IOEs in the column I/O block can have one io_datain input (combinatorial or registered) and
one comb_io_datain (combinatorial) input.
21 Data &
Control Signals
from Logic Array (1)
Column I/O
Block Contains
up to Three IOEs
I/O Block
Local Interconnect
IO_datain[2:0] &
comb_io_datain[2..0]
(2)
R4 Interconnects
LAB Local
Interconnect
C4 Interconnects
21
LAB
LAB
LAB
io_clk[5..0]
Column I/O Block


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