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EP1C6F256C7 Datasheet(PDF) 1 Page - Altera Corporation

Part # EP1C6F256C7
Description  Cyclone FPGA Family
Download  94 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1C6F256C7 Datasheet(HTML) 1 Page - Altera Corporation

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®
Altera Corporation
1
Cyclone
FPGA Family
March 2003, ver. 1.1
Data Sheet
DS-CYCLONE-1.1
Introduction
Preliminary
Information
The CycloneTM field programmable gate array family is based on a 1.5-V,
0.13-
µm, all-layer copper SRAM process, with densities up to 20,060 logic
elements (LEs) and up to 288 Kbits of RAM. With features like phase-
locked loops (PLLs) for clocking and a dedicated double data rate (DDR)
interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory
requirements, Cyclone devices are a cost-effective solution for data-path
applications. Cyclone devices support various I/O standards, including
LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz,
32-bit peripheral component interconnect (PCI), for interfacing with and
supporting ASSP and ASIC devices. Altera also offers new low-cost serial
configuration devices to configure Cyclone devices.
Features...
2,910 to 20,060 LEs, see Table 1
Up to 294,912 RAM bits (36,864 bytes)
Supports configuration through low-cost serial configuration device
Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
Support for 66-MHz, 32-bit PCI standard
Low speed (311 Mbps) LVDS I/O support
Up to two PLLs per device provide clock multiplication and phase
shifting
Up to eight global clock lines with six clock resources available per
logic array block (LAB) row
Support for external memory, including DDR SDRAM (133 MHz),
FCRAM, and single data rate (SDR) SDRAM
Support for multiple intellectual property (IP) cores, including
AlteraMegaCorefunctions and Altera Megafunctions Partners
Program (AMPPSM) megafunctions
Note to Table 1:
(1)
This parameter includes global clock pins.
Table 1. Cyclone Device Features
Feature
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
LEs
2,910
4,000
5,980
12,060
20,060
M4K RAM blocks (128
× 36 bits)
131720
5264
Total RAM bits
59,904
78,336
92,160
239,616
294,912
PLLs
12
222
Maximum user I/O pins (1)
104
301
185
249
301


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