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M54HCT563 Datasheet(PDF) 1 Page - STMicroelectronics

Part No. M54HCT563
Description  OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HCT563 INVERTING - HCT573 NON INVERTING
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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M54HCT563 Datasheet(HTML) 1 Page - STMicroelectronics

 
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M54/74HCT563
M54/74HCT573
October 1993
HCT563 INVERTING - HCT573 NON INVERTING
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT
B1R
(Plastic Package)
ORDER CODES :
M54HCTXXXF1R
M74HCTXXXM1R
M74HCTXXXB1R
M74HCTXXXC1R
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
PIN CONNECTION (top view)
.
HIGH SPEED
tPD = 18 ns (TYP.) AT VCC =5 V
.
LOW POWER DISSIPATION
ICC =4
µA (MAX.) AT TA =25 °C
.
COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.) VIL = 0.8V (MAX.)
.
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
IOL =
IOH= 6 mA (MIN.)
.
BALANCED PROPAGATION DELAYS
tPLH =tPHL
.
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS563/573
DESCRIPTION
The M54/74HCT563 and M54HCT573 are high
speed CMOS OCTAL LATCH WITH 3-STATE
OUTPUTS fabricated with silicon gate C
2MOS
technology.
These ICs achive the high speed operation similar
to equivalent LSTTL while maintaining the CMOS
low power dissipation.
These 8 bit D-Type latches are controlled by a latch
enable input (LE) and a output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely or
inversely. When the LE is taken low, the Q outputs
will be latched precisely or inversely at the logic level
of D input data. While the OE input is at low level,
the eight outputs will be in a normal logic state (high
or low logic level) and while high level the outpts will
be in a high impedance state.
The
application
designer
has
a
choise
of
combination of inverting and non inverting outputs.
This integrated circuit has input and output
characteristics that are fully compatible with 54/74
LSTTL logic families. M54/74HCT devices are
designed to directly interface HSC
2MOS systems
with TTL and NMOS components. They are also
plug in replacements for LSTTL devices giving a
reduction of power consumption.
All inputs are equipped with protection circuits
against discharge and transient excess voltage.
HCT563
HCT573
HCT563
HCT573
1/13


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