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--Preliminary, Confidential, Proprietary--
Acer Laboratories Inc.
M512x : Mega I/O Controller with PnP
Page 6
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, ROC Tel: 886-(02) 762-8800
Fax: 762-6060
Section 2 : Pin Description
2.1 Pinout Diagram
PWG
ROMCSJ
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
CIO25
CIO24
CIO23
CIO22
CIO21
CIO20
CIO17/I2C_DAT
CIO16/I2C_CLK
CIO15/P20
VDD
CIO14/P21
CIO13/IRTX
CIO12/IRRX
CIO11/IRQIN2
CIO10/IRQIN1
GND
MCLK
MDAT
KCLK
KDAT
IOCHRDY
TC
DRQ3
DACK3J
DRQ2
DACK2J
DRQ1
DACK1J
DRQ0
DACK0J
GND
DRVDEN0
DRVDEN1
MOT0J
DRV1J
DRV0J
MOT1J
GND
DIRJ
STEPJ
WDATAJ
WGATEJ
HDSELJ
INDEXJ
TRK0J
WPROTJ
RDATAJ
DSKCHGJ
MID1
MID0
VDD
14CLKI
CIO30/KBCCLK
CIO31/CS0J
CIO32/CS1J
PDIR/PS2DRV
SA[13]
SA[14]
SA[15]
CIO33/ALT_KCLK
CIO34/ALT_KDAT
CIO35/ALT_MCLK
CIO36/ALT_MDAT
CIO37/ALT_KBC
X24TAL1
X24TAL2
CLK01
CLK02
ROMOEJ
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
ALi
M512x
Figure 2-1. M512x Pin Diagram