--Preliminary, Confidential, Proprietary--
Acer Laboratories Inc.
M512x : Mega I/O Controller with PnP
Page 58
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, ROC Tel: 886-(02) 762-8800
Fax: 762-6060
5.2 Programmable Baud Generator
The UART contains two independently programmable baud
generators. The 24-MHz crystal oscillator frequency input is
divided by 13, resulting in a frequency of 1.8462-MHz. This
is sent to each baud generator and divided by the divisor for
the associated UART.
The output frequency of the baud
generator is 16 X the baud rate, [divisor # = (frequency
input) / (baud rate x 16)].
The output of each baud
generator drives the transmitter and receiver sections of the
associated serial channel.
Two 8-bit latches per channel
store the divisor in a 16-bit binary format.
These divisor
latches must be loaded during initialization to ensure proper
operation of the baud generator. Upon loading either of the
divisor latches, a 16-bit baud counter is loaded.
Table 5-5 provides decimal divisors to use with crystal
frequencies of 24-MHz.
The oscillator input to the chip
should always be 24-MHz to ensure that the FDC timing is
accurate and that the UART divisors are compatible with
existing
software.
Using
a
divisor
of
zero
is
not
recommended.
5.3 Line Status Register (LSR)
This register provides status information to the CPU
concerning the data transfer.
LSR is intended for read
operations only. Writing to this register is not recommended
as this operation is only used for factory testing.
Table 5-4
Line Status Register Function Definition
Bit
Function
7
In 16450 mode, this bit is set to 0. In FIFO, LSR7 is set when there is at least one parity error, framing
error or break indication in the FIFO LSR7 is cleared when the CPU reads the LSR, if there are no
subsequent errors in the FIFO.
6
This bit changes its function depending on whether the device is operating in XT/AT mode. When in
the AT mode, this bit is the transmitter empty (TEMT) indicator. It is set to 1 whenever the transmitter
holding register (THR) and the transmitter shift register (TSR) are both empty. It is reset to 0 whenever
either the THR or TSR contains a data character.
5
Transmitter holding register empty (THRE) indicator. It indicates that the UART is ready to accept a
new character for transmission. It also causes the UART to issue an interrupt to the CPU when the
THRE interrupt enable is set high. It is set to 1 when a character is transferred from the THRE into
TSR. It is reset to 0 whenever the CPU loads the THRE.
4
Break interrupt (BI) indicator. It is set to 1 when the received data input is held in the spacing (logic 0)
state for longer than a full word transmission time (that is, the total time of start bit data bits parity
stop bits). It is reset whenever the CPU reads the contents of the LSR. Restarting after a break is
received requires the SIN pin to be logical 1 for at least 1/2-bit time.
3
Framing error (FE) indicator. This bit indicates that the received character did not have a valid stop bit.
It is set to 1 whenever the stop bit following the last data bit or parity bit is a logic 0 (spacing level).
The FE indicator is reset whenever the CPU reads the contents of LSR.
The UART tries to
resynchronize after a framing error. To do this, it assumes that the FE was due at the next start bit, so
it samples this start bit twice and then takes in the data.
2
Parity error (PE) indicator. This bit indicates that the received data character does not have the correct
even or odd parity, as selected by the even-parity-select bit. It is set to 1 upon detection of a parity
error and reset to 0 whenever the CPU reads the contents of the LSR.
1
Overrun error (OE) indicator. It indicates that data in the RBR was not read by the CPU before the next
data was transferred into the RBR, thereby destroying the previous data. It is set to 1 upon detection of
an overrun condition and reset to 0 whenever the CPU reads the contents of the LSR.
0
Receive data ready (DR) indicator. It is set to 1 whenever a complete incoming character has been
received and transferred into the RBR. It is reset to 0 by reading the data in the RBR.
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