MITSUBISHI ELECTRIC

1997-5-28D.rev

MITSUBISHI <Dig./Ana. INTERFACE>

M62398P,FP

8BIT 12CH I C BUS D–A CONVERTER WITH BUFFER AMPLIFIERS

( / 7)

2

6

TIMING CHART (MODEL)

•Start condition ……… With SCL at HIGH,SDA line goes from HIGH to LOW

•Stop condition ……… With SCL at HIGH,SDA line goes from LOW to HIGH

(*Under normal circumstances,SDA is changed when SCL is LOW)

•Acknowledge bit …… The receiving IC has to pull down SDA line whenever receive slave data.

(The transmitting IC releases the SDA line just then transmit 8bit data.)

•DAC data bite to stop condition

SDA

SCL

R

DAC

output

1

2

A

3

4

5

6

7

W

•start condition to slave address bite

start condition

stop condition

SDA

SCL

R

DAC

output

1

2

A

3

4

5

6

7

8

•sub address bite

SDA

SCL

R

DAC

output

1

2

A

3

4

5

6

7

8