LTC2431 datasheet(11/40 Pages) LINER

Part #	LTC2431

Description	20-Bit No Latency Delta-Sigma ADCs with Differential Input and Differential Reference

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LTC2430/LTC2431

11

24301f

CONVERTER OPERATION

Converter Operation Cycle

The LTC2430/LTC2431 are low power, delta-sigma analog-

to-digital converters with an easy-to-use 3-wire serial inter-

face(seeFigure1).Their operationismadeupofthreestates.

The converters’ operating cycle begins with the conversion,

followed by the low power sleep state and ends with the data

output (see Figure 2). The 3-wire interface consists of serial

data output (SDO), serial clock (SCK) and chip select (CS).

Initially, the LTC2430/LTC2431 perform a conversion.

Once the conversion is complete, the device enters the

sleep state. The part remains in the sleep state as long as

CS is HIGH. While in this sleep state, power consumption

is reduced by nearly two orders of magnitude. The conver-

sion result is held indefinitely in a static shift register while

the converter is in the sleep state.

Once CS is pulled LOW, the device exits the low power mode

and enters the data output state. If CS is pulled HIGH be-

fore the first rising edge of SCK, the device returns to the

low power sleep mode and the conversion result is still held

in the internal static shift register. If CS remains LOW after

the first rising edge of SCK, the device begins outputting

the conversion result. Taking CS high at this point will

terminate the data output state and start a new conversion.

There is no latency in the conversion result. The data out-

put corresponds to the conversion just performed. This

result is shifted out on the serial data out pin (SDO) under

the control of the serial clock (SCK). Data is updated on the

falling edge of SCK allowing the user to reliably latch data

on the rising edge of SCK (see Figure 3). The data output

state is concluded once 24 bits are read out of the ADC or

when CS is brought HIGH. The device automatically initiates

a new conversion and the cycle repeats.

Through timing control of the CS and SCK pins, the

LTC2430/LTC2431 offer several flexible modes of

operation (internal or external SCK and free-running

conversion modes). These various modes do not require

programming configuration registers; moreover, they do

not disturb the cyclic operation described above. These

modes of operation are described in detail in the Serial

Interface Timing Modes section.

Conversion Clock

A major advantage the delta-sigma converter offers over

conventional type converters is an on-chip digital filter

(commonly implemented as a Sinc or Comb filter). For

high resolution, low frequency applications, this filter is

typically designed to reject line frequencies of 50Hz or

60Hz plus their harmonics. The filter rejection perfor-

mance is directly related to the accuracy of the converter

system clock. The LTC2430/LTC2431 incorporate a highly

accurate on-chip oscillator. This eliminates the need for

external frequency setting components such as crystals or

oscillators. Clocked by the on-chip oscillator, the LTC2430/

LTC2431 achieve a minimum of 110dB rejection at the line

frequency (50Hz or 60Hz

±2%).

Ease of Use

The LTC2430/LTC2431 data output has no latency, filter

settling delay or redundant data associated with the

conversion cycle. There is a one-to-one correspondence

between the conversion and the output data. Therefore,

multiplexing multiple analog inputs is easy.

The LTC2430/LTC2431 perform offset and full-scale cali-

brations in every conversion cycle. This calibration is trans-

parent to the user and has no effect on the cyclic operation

described above. The advantage of continuous calibration

is extreme stability of offset and full-scale readings with

respect to time, supply voltage change and temperature

drift.

Figure 2. LTC2430/LTC2431 State Transition Diagram

CONVERT

SLEEP

DATA OUTPUT

2431 F02

TRUE

FALSE

CS = LOW

AND

SCK

APPLICATIO S I FOR ATIO

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