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ADM1073ARU Datasheet(PDF) 18 Page - Analog Devices |
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ADM1073ARU Datasheet(HTML) 18 Page - Analog Devices |
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18 / 24 page  ADM1073 Rev. 0| Page 18 of 24 FUNCTIONALITY AND TIMING LIVE INSERTION The timing waveforms associated with the live insertion of a plug-in board using the ADM1073 are shown in Figure 36. The long connector pins are the first to make connection, and the GND − VEE potential climbs to 48 V. As this voltage is applied, the voltage at the VIN pin ramps to a constant 12.3 V and is held at this level with the shunt resistor and external resistor combination at the VIN pin. In this case, the connection pins are staggered so that the R1/R2 and R3/R4 resistor dividers are the last to connect to the backplane. This means that VUV and VOV begin to ramp after the other pins connect. Note that staggered connector pins are optional, because an internal time filter is included on the UV pin. When VUV crosses the undervoltage rising threshold, it is now inside the operating voltage window and the −48 V supply must be applied to the load. The SPLYGD output is asserted and after a time delay, tPOR, the ADM1073 begins to ramp up the gate drive. When the voltage on the SENSE pin reaches 100 mV (the analog current limit level), the gate drive is held constant. When the board capacitance is fully charged, the sense voltage begins to drop below the analog current limit voltage and the gate voltage is free to ramp up further. The gate voltage eventually climbs to its maximum value of 12.3 V and the PWRGD output is asserted. Figure 37 shows some typical startup waveforms. tPOR VLKO VUVR –48V RTN – VEE VIN VUV GATE SENSE VOUT SPLYGD PWRGD Figure 36. Timing Waveforms Associated with a Live Insertion Event Figure 37. Typical Startup Sequence (Ch1 = GATE; Ch2 = SENSE; Ch3 = PWRGD; Ch4 = SPLYGD) OVERVOLTAGE AND UNDERVOLTAGE FAULTS The waveforms for an overvoltage glitch are shown in Figure 38. When VOV glitches above the overvoltage threshold of 1.93 V, an overvoltage condition is detected and the GATE voltage is pulled low. VOV begins to drop back toward the operating voltage window, and the GATE drive is restored when the overvoltage falling threshold (1.93 V minus preset OV hysteresis level) is reached. Figure 38 illustrates the ADM1073’s reactions to an overvoltage condition. Figure 38. Timing Waveforms Associated with an Overvoltage Fault (Ch1 = GATE; Ch2 = OV; Ch3 = PWRGD; Ch 4 = SPLYGD) |
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