CY28372
Document #: 38-07533 Rev. *A
Page 6 of 18
Bit 3
HW
Latched FS3 input
Latched FS[3:0] inputs. These bits are read-only.
Bit 2
HW
Latched FS2 input
Bit 1
HW
Latched FS1 input
Bit 0
HW
Latched FS0 input
Byte 6
Bit
@Pup
Name
Description
Bit 7
0
Reserved
Reserved
Bit 6
0
Reserved
Reserved
Bit 5
0
PCIF0
PCIF0 functionality when PCI_STP# is LOW
0: Free running, 1: Stop
Bit 4
0
PCIF1
PCIF1 functionality when PCI_STP# is LOW
0: Free running, 1: Stop
Bit 3
1
CPUT0/CPUC0
CPU[T/C]0 functionality when CPU_STP# is LOW
0: Free running, 1: Stop (three-state)
Bit 2
0
CPUT1
CPUT1 functionality when CPU_STP# is LOW
0: Free running, 1: Stop (three-state)
Bit 1
1
CPUT0/CPUC0
CPU[T/C]0 Output Enable/Disable
Bit 0
1
CPUT1
CPUT1 Output Enable/Disable
Byte 7
Bit
@Pup
Name
Description
Bit 7
1
PCIF1
PCIF1 Output Enable/Disable
Bit 6
1
PCIF0
PCIF0 Output Enable/Disable
Bit 5
1
PCI_5
PCI_5 Output Enable/Disable
Bit 4
1
PCI_4
PCI_4 Output Enable/Disable
Bit 3
1
PCI_3
PCI_3 Output Enable/Disable
Bit 2
1
PCI_2
PCI_2 Output Enable/Disable
Bit 1
1
PCI_1
PCI_1 Output Enable/Disable
Bit 0
1
PCI_0
PCI_0 Output Enable/Disable
Byte 8
Bit
@Pup
Name
Pin Description
Bit 7
1
Vendor_ID3
Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Bit 6
0
Vendor_ID2
Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Bit 5
0
Vendor _ID1
Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Bit 4
0
Vendor _ID0
Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Bit 3
0
Revision_ID3
Revision ID bit[3]
Bit 2
0
Revision_ID2
Revision ID bit[2]
Bit 1
0
Revision_ID1
Revision ID bit[1]
Bit 0
0
Revision_ID0
Revision ID bit[0]
Byte 9
Bit
@Pup
Name
Description
Bit 7
1
PD#
Power-down Enable
Bit 6
0
Reserved
Reserved
Bit 5
1
48MHz
48-MHz Output Control
Byte 5 (continued)
Bit
@Pup
Name
Description