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CY28372
Document #: 38-07533 Rev. *A
Page 5 of 18
Device Configuration Map
Data Bytes 0 to 3: Reserved for ZDB Registers
28
Acknowledge from slave
21:27
Slave address – 7 bits
29
Stop
28
Read = 1
29
Acknowledge from slave
30:37
Data byte from slave – 8 bits
38
Not Acknowledge
39
Stop
Table 4. Byte Read and Byte Write Protocol (continued)
Byte Write Protocol
Byte Read Protocol
Bit
Description
Bit
Description
Byte 4
Bit
@Pup
Name
Description
Bit 7
1
Frequency Select Register
(FS3)
[7..4]
CPU
ZCLK
AGPPCI
Bit2 = 0
0000
133.3
66.7
66.733.3
0001
133.3
66.7
50.033.3
0010
133.3
100.0
66.733.3
0011
133.3
100.0
50.033.3
0100
133.3
133.3
66.733.3
0101
133.3
133.3
50.033.3
0110
133.3
166.6
66.733.3
0111
133.3
166.6
55.533.3
1000
100.0
66.7
66.733.3
1001
100.0
66.7
50.033.3
1010
100.0
100.0
66.733.3
1011
100.0
100.0
50.033.3
1100
100.0
133.3
66.733.3
1101
100.0
133.3
50.033.3
1110
111.0
166.5
66.633.3
1111
111.0
166.5
55.533.3
Bit2 = 1
0000
114.5
95.4
63.631.8
0001
120.0
100.0
66.733.3
0010
133.3
83.3
66.733.3
0011
133.3
111.1
74.133.3
0100
133.3
133.3
83.333.3
0101
145.7
116.6
64.832.4
0110
150.0
100.0
66.733.3
0111
166.6
111.1
66.733.3
1000
111.1
133.3
66.733.3
1001
137.4
137.4
68.734.4
1010
144.9
144.9
64.432.2
1011
150.0
150.0
66.733.3
1100
155.1
124.1
68.934.5
1101
166.6
133.3
66.733.3
1110
180.1
135.1
67.633.8
1111
200.0
133.3
66.733.3
Bit 6
0
Frequency Select Register
(FS2)
Bit 5
0
Frequency Select Register
(FS1)
Bit 4
0
Frequency Select Register
(FS0)
Bit 3
0
FS_Override
Frequency Selection Source:
0 = Select through hardware strapping, latched inputs
1 = Select through I2C
Bit 2
0
Frequency Select Register Most significant bit of I2C Frequency Select Register
Bit 1
1
Spread Spectrum Control
0 = Normal, 1 = Spread Spectrum enable
Bit 0
0
Output Disable
0 = Normal, 1 = three-state all outputs
Byte 5
Bit
@Pup
Name
Description
Bit 7
0
Reserved
Reserved
Bit 6
0
Reserved
Reserved
Bit 5
0
Reserved
Reserved
Bit 4
0
Reserved
Reserved
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