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TMS626812B Datasheet(PDF) 2 Page - Texas Instruments

Part No. TMS626812B
Description  1,048,576 BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS626812B Datasheet(HTML) 2 Page - Texas Instruments

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TMS626812B
1 048 576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
2
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
description
The TMS626812B is a high-speed, 16 777 216-bit synchronous dynamic random-access memory (SDRAM)
device organized as follows:
D Two banks of 1048576 words with 8 bits per word (TMS626812B)
All inputs and outputs of the TMS626812B series are compatible with the LVTTL interface.
The SDRAM employs state-of-the-art technology for high performance, reliability, and low power. All inputs and
outputs are synchronized with the CLK input to simplify system design and enhance the use with high-speed
microprocessors and caches.
The TMS626812B SDRAM is available in a 400-mil, 44-pin surface-mount thin small–outine package (TSOP)
(DGE suffix).
functional block diagram
CLK
CKE
CS
DQM
RAS
CAS
W
A0 – A11
Control
Mode Register
Array Bank T
Array Bank B
DQ
Buffer
12
DQ0 – DQ7
8
operation
All inputs of the ’626812B SDRAM are latched on the rising edge of the system (synchronous) clock. The
outputs, DQx, also are referenced to the rising edge of CLK. The ’626812B has two banks that are accessed
independently. A bank must be activated before it can be accessed (read from or written to). Refresh cycles
refresh both banks alternately.
Six basic commands or functions control most operations of the ’626812B:
D Bank activate/row-address entry
D Column-address entry/write operation
D Column-address entry/read operation
D Bank deactivate
D Auto-refresh
D Self-refresh


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