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TMS626812B Datasheet(PDF) 17 Page - Texas Instruments |
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TMS626812B Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 40 page  TMS626812B 1 048 576 BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS693A – OCTOBER 1997 – REVISED APRIL 1998 17 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 14) PARAMETER MIN MAX UNIT Ci(S) Input capacitance, CLK 2.5 4 pF Ci(AC) Input capacitance, A0 – A11, CS, DQM, RAS, CAS, W 2.5 5 pF Ci(E) Input capacitance, CKE 5 pF Co Output capacitance 4 6.5 pF NOTE 14: VCC = 3.3 ± 0.3 V and bias on pins under test is 0 V. ac timing requirements†‡ ’626812B-8 ’626812B-8A ’626812B-10 UNIT MIN MAX MIN MAX MIN MAX UNIT tCK2 Cycle time, CLK, CAS latency = 2 10 15 15 ns tCK3 Cycle time, CLK, CAS latency = 3 8 8 10 ns tCH Pulse duration, CLK high 3 3 3 ns tCL Pulse duration, CLK low 3 3 3 ns tAC2 Access time, CLK high to data out, CAS latency = 2 (see Note 15) 6 7 7.5 ns tAC3 Access time, CLK high to data out, CAS latency = 3 (see Note 15) 6 6 7.5 ns tOH Hold time, CLK high to data out (with 50-pF load) 3 3 3 ns tLZ Delay time, CLK high to DQ in low-impedance state (see Note 16) 1 1 2 ns tHZ Delay time, CLK high to DQ in high-impedance state (see Note 17) 8 8 8 ns tIS Setup time, address, control, and data input 2 2 2 ns tIH Hold time, address, control, and data input 1 1 1 ns tCESP Power-down/self-refresh exit time (see Note 18) 8 8 10 ns tRAS Delay time, ACTV command to DEAC or DCAB command 48 100 000 48 100 000 50 100 000 ns tRC Delay time, ACTV, REFR, or SLFR exit to ACTV, MRS, REFR, or SLFR command 68 68 80 ns tRCD Delay time, ACTV command to READ, READ-P, WRT, or WRT-P command (see Note 19) 20 20 30 ns tRP Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command 20 20 30 ns tRRD Delay time, ACTV command in one bank to ACTV command in the other bank 16 16 20 ns † See Parameter Measurement Information for load circuits. ‡ All references are made to the rising transition of CLK, unless otherwise noted. NOTES: 15. tAC is referenced from the rising transition of CLK that precedes the data-out cycle. For example, the first data-out tAC is referenced from the rising transition of CLK0 that is CAS latency minus one cycle after the READ command. Access time is measured at output reference level 1.4 V. 16. tLZ is measured from the rising transition of CLK that is CAS latency minus one cycle after the READ command. 17. tHZ MAX defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 18. See Figure 18 and Figure 19. 19. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS. |
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