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TMS626812B Datasheet(PDF) 16 Page - Texas Instruments

Part No. TMS626812B
Description  1,048,576 BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS626812B Datasheet(HTML) 16 Page - Texas Instruments

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electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted)
(see Note 6)
PARAMETER
TEST CONDITIONS
’626812B-8
’626812B-8A
’626812B-10
UNIT
PARAMETER
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
VOH
High-level output voltage
IOH = –4 mA
2.4
2.4
2.4
V
VOL
Low-level output voltage
IOL = 4 mA
0.4
0.4
0.4
V
II
Input current (leakage)
0 V
≤ VI ≤ VCC + 0.3 V,
All other pins = 0 V to VCC
±10
±10
±10
µA
IO
Output current (leakage)
0 V
≤ VO ≤ VCC + 0.3 V,
Output disabled
±10
±10
±10
µA
ICC1
Operating current
Burst length = 1, tRC w tRC MIN
IOH/IOL 0 mA 1 bank activated
CAS latency = 2
95
95
85
mA
ICC1
Operating current
IOH/IOL = 0 mA, 1 bank activated
(see Notes 7, 8, and 9)
CAS latency = 3
100
100
90
mA
ICC2P
Precharge standby current
CKE
v VIL MAX, tCK = 15 ns (see Note 10)
1
1
1
mA
ICC2PS
gy
in power-down mode
CKE and CLK
v VIL MAX, tCK = ∞ (see Note 11)
1
1
1
mA
ICC2N
Precharge standby current
CKE
w VIH MIN, tCK = 15 ns (see Note 10)
30
30
30
mA
ICC2NS
gy
in non-power-down mode
CKE
w VIH MIN, CLK v VIL MAX, tCK = ∞ (see Note 11)
2
2
2
mA
ICC3P
Active standby current in
CKE
v VIL MAX, tCK = 15 ns (see Notes 7 and 10)
3
3
3
mA
ICC3PS
y
power-down mode
CKE and CLK
v VIL MAX, tCK = ∞ (see Notes 7 and 11)
3
3
3
mA
ICC3N
Active standby current in
CKE
w VIH MIN, tCK = 15 ns (see Notes 7 and 10)
40
40
40
mA
ICC3NS
y
non-power-down mode
CKE
w VIH MIN, CLK v VIL MAX, tCK = ∞ (see Notes 7 and 11)
10
10
10
mA
ICC4
Burst current
Page burst, IOH/IOL = 0 mA
All banks activated nCCD 1 cycle
CAS latency = 2
140
140
130
mA
ICC4
Burst current
All banks activated, nCCD = 1 cycle
(see Notes 12 and 13)
CAS latency = 3
150
150
140
mA
ICC5
Auto refresh current
tRC v tRC MIN (see Note 11)
CAS latency = 2
90
90
80
mA
ICC5
Auto-refresh current
tRC v tRC MIN (see Note 11)
CAS latency = 3
95
95
85
mA
ICC6
Self-refresh current
CKE
v VIL MAX
0.400
0.400
0.400
mA
NOTES:
6. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid.
7. Only one bank is activated.
8. tRC = MIN
9. Control, DQ, and address inputs change state only twice during tRC.
10. Control, DQ, and address inputs change state only once every 30 ns.
11. Control, DQ, and address inputs do not change (stable).
12. Control, DQ, and address inputs change state only once every cycle.
13. Continuous burst access, nCCD = 1 cycle.


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