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TMS626812B Datasheet(PDF) 14 Page - Texas Instruments

Part No. TMS626812B
Description  1,048,576 BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS626812B Datasheet(HTML) 14 Page - Texas Instruments

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TMS626812B
1 048 576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
14
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
interrupted bursts (continued)
DQ
CLK
C1 + 3
C1 + 2
C1 + 1
C1
C0 + 1
C0
nCCD = 2 Cycles
WRT Command at
Column Address C0
Interrupting
WRT Command
at Column Address C1
NOTE A: For this example, assume burst length = 4.
Figure 6. Write Burst Interrupted by Write Command
CLK
DQ
D
D
Ignored
nCCD = 3 Cycles
WRT Command
DQM
tWR
Ignored
Interrupting
DEAC or DCAB
Command
NOTE A: For this example, assume burst length = 4.
Figure 7. Write Burst Interrupted by DEAC/DCAB Command
power-up sequence
Device initialization must be performed after a power up to the full VCC level. After power is established, a 200-µs
interval is required (with no inputs other than CLK). After this interval, both banks of the device must be
deactivated. Eight REFR commands must be performed and the mode register must be set to complete the
device initialization.


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