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TMS626812B Datasheet(PDF) 1 Page - Texas Instruments

Part No. TMS626812B
Description  1,048,576 BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
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TMS626812B Datasheet(HTML) 1 Page - Texas Instruments

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TMS626812B
1 048 576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS693A – OCTOBER 1997 – REVISED APRIL 1998
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
SYNCHRONOUS
CLOCK
CYCLE TIME
ACCESS TIME
(CLOCK TO
OUTPUT)
REFRESH
TIME
INTERVAL
tCK3
(CL† =3)
tCK2
(CL = 2)
tAC3
(CL = 3)
tAC2
(CL = 2)
’626812B-8
8 ns
10 ns
6 ns
6 ns
64 ms
’626812B-8A
8 ns
15 ns
6 ns
7 ns
64 ms
’626812B-10
10 ns
15 ns
7.5 ns
7.5 ns
64 ms
† CL = CAS latency
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D Organization
1048576 by 8 Bits by 2 Banks
D 3.3-V Power Supply (±10% Tolerance)
D Two Banks for On-Chip Interleaving
(Gapless Accesses)
D High Bandwidth – Up to 125-MHz Data
Rates
D CAS Latency (CL) Programmable to
2 or 3 Cycles From Column-Address Entry
D Burst Sequence Programmable to Serial or
Interleave
D Burst Length Programmable to 1, 2, 4, or 8
D Chip Select and Clock Enable for Enhanced
System Interfacing
D Cycle-by-Cycle DQ Bus Mask Capability
D Auto-Refresh and Self-Refresh Capabilities
D 4K Refresh (Total for Both Banks)
D High-Speed, Low-Noise, Low-Voltage TTL
(LVTTL) Interface
D Power-Down Mode
D Compatible With JEDEC Standards
D Pipeline Architecture
D Temperature Ranges
Operating, 0
°C to 70°C
Storage, – 55
°C to 150°C
D Intel PC100 Compliant (-8A, -8, and
-10 Devices)
D Performance Ranges:
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VSS
DQ7
VSSQ
DQ6
VCCQ
DQ5
VSSQ
DQ4
VCCQ
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VCC
DQ0
VSSQ
DQ1
VCCQ
DQ2
VSSQ
DQ3
VCCQ
NC
NC
W
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VCC
TMS626812B
DGE PACKAGE
( TOP VIEW )
PIN NOMENCLATURE
A0 – A10 Address Inputs
A0 – A10 Row Addresses
A0 – A8 Column Addresses (for TMS626812B)
A10 Automatic-Precharge Select
A11
Bank Select
CAS
Column-Address Strobe
CKE
Clock Enable
CLK
System Clock
CS
Chip Select
DQ[0 :7]
SDRAM Data Input / Output (TMS626812B)
DQM
Data-Input / Data-Output Mask Enable
NC
No External Connect
RAS
Row-Address Strobe
VCC
Power Supply (3.3-V Typical)
VCCQ
Power Supply for Output Drivers
(3.3-V Typical)
VSS
Ground
VSSQ
Ground for Output Drivers
W
Write Enable
Copyright
© 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.


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