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TMS626162A Datasheet(PDF) 2 Page - Texas Instruments

Part No. TMS626162A
Description  524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
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TMS626162A Datasheet(HTML) 2 Page - Texas Instruments

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TMS626162A
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS692B – JULY 1997 – REVISED MARCH 1998
2
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
description (continued)
All inputs and outputs of the TMS626162A series are compatible with the LVTTL interface.
The SDRAM employs state-of-the-art technology for high performance, reliability, and low power. All inputs and
outputs are synchronized with the CLK input to simplify system design and enhance use with high-speed
microprocessors and caches.
The TMS626162A SDRAM is available in a 400-mil, 50-pin surface-mount TSOP package (DGE suffix).
functional block diagram
CLK
CKE
CS
DQMx
RAS
CAS
W
A0 – A11
Control
Mode Register
Array Bank T
Array Bank B
DQ
Buffer
DQ0 – DQ15
16
12
operation
All inputs to the ’626162A SDRAM are latched on the rising edge of the system (synchronous) clock. The
outputs, DQ0 – DQ15, are also referenced to the rising edge of CLK. The ’626162A has two banks that are
accessed independently. A bank must be activated before it can be accessed (read from or written to). Refresh
cycles refresh both banks alternately.
Six basic commands or functions control most operations of the ’626162A:
D Bank activate/row-address entry
D Column-address entry/write operation
D Column-address entry/read operation
D Bank deactivate
D Auto-refresh
D Self-refresh
Additionally, operations can be controlled by three methods: using chip select (CS) to select / deselect the
devices, using data/output mask enables (DQMx) to enable/mask the DQ signals on a cycle-by-cycle basis, or
using clock enable (CKE) to suspend the system clock (CLK) input. The device contains a mode register that
must be programmed for proper operation.
Table 1 through Table 3 show the various operations that are available on the ’626162A. These truth tables
identify the command and/or operations and their respective mnemonics. Each truth table is followed by a
legend that explains the abbreviated symbols. An access operation refers to any read or write command in
progress at cycle n. Access operations include the cycle upon which the read or write command is entered and
all subsequent cycles through the completion of the access burst.


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