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TMS320AV7110 Datasheet(PDF) 3 Page - Texas Instruments |
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TMS320AV7110 Datasheet(HTML) 3 Page - Texas Instruments |
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DSP TMS320AV7110 Revision 3.1 10/08/99 22:18 Page 3 7.8.2 True Size Display Mode ........................................................................................................ 39 7.8.3 Video display synchronization mode..................................................................................... 40 7.8.4 Vsync reset and split VBV buffer...........................................................................................40 8. OSD & GRAPHICS ACCELERATION........................................................................................... 41 8.1 OSD .............................................................................................................................................. 41 8.1.1 Description............................................................................................................................ 41 8.1.2 OSD data storage.................................................................................................................. 42 8.2 SETTING UP AN OSD WINDOW ...................................................................................................... 42 8.2.1 CAM Memory ........................................................................................................................ 42 8.2.2 Window Attribute Memory ....................................................................................................43 8.2.3 Color Look Up Table ............................................................................................................ 43 8.2.4 Blending and Transparency ..................................................................................................43 8.2.5 Hardware Cursor .................................................................................................................. 45 8.2.6 Output Channels ................................................................................................................... 45 8.3 THE BITBLT HARDWARE............................................................................................................... 46 8.3.1 Sources and Destinations...................................................................................................... 47 8.3.2 Source and Destination Window Formats ............................................................................ 47 8.3.3 Transparency ........................................................................................................................ 47 9. VIDEO OUTPUT INTERFACES ..................................................................................................... 48 9.1 ANALOG VIDEO OUTPUT - NTSC/PAL ENCODER MODULE ........................................................... 48 9.2 TELETEXT AND WIDE SCREEN SIGNALING (WSS) INSERTION (PAL MODE ONLY)......................... 48 9.2.1 Teletext insertion into PAL CVBS ......................................................................................... 48 9.2.2 WSS insertion into CVBS ...................................................................................................... 49 9.2.3 Insertion mode ...................................................................................................................... 49 9.3 CLOSED CAPTION, EXTENDED DATA SERVICES, AND VIDEO ASPECT RATIO IDENTIFICATION SIGNAL INSERTION (NTSC MODE ONLY) ................................................................................................... 49 9.4 DIGITAL VIDEO OUTPUT ................................................................................................................ 50 9.4.1 PAL Mode Digital Video Output........................................................................................... 50 9.4.2 NTSC Mode Digital Video Output ........................................................................................ 50 10. AUDIO DECODER ........................................................................................................................ 52 10.1 FEATURES ...................................................................................................................................... 52 10.2 PCM AUDIO OUTPUT..................................................................................................................... 53 10.2.1 Using an External Audio PLL ...............................................................................................55 10.3 PCM BYPASS................................................................................................................................. 55 10.4 ELEMENTARY STREAM PLAYBACK ................................................................................................ 56 10.5 SPDIF AUDIO OUTPUT .................................................................................................................. 56 11. SYNCHRONIZATION................................................................................................................... 57 11.1 SYSTEM TIME CLOCK .................................................................................................................... 57 11.2 STARTUP SYNCHRONIZATION......................................................................................................... 57 11.3 RUNTIME SYNCHRONIZATION ........................................................................................................ 57 11.4 AUDIO SYNCHRONIZATION............................................................................................................. 58 11.5 VIDEO SYNCHRONIZATION............................................................................................................. 58 11.6 AUDIO-VIDEO SYNCHRONIZATION (LIP-SYNC)................................................................................ 59 12. EXTENSION BUS INTERFACE (EBI)........................................................................................ 60 12.1 ADDRESS RANGE AND WAIT STATE OF CHIP SELECT..................................................................... 60 12.2 EBI READ AND WRITE CYCLES ..................................................................................................... 61 12.3 INTERRUPTS ................................................................................................................................... 61 12.4 THE EXTWAIT SIGNAL ................................................................................................................ 62 12.5 THE EXTENSION BUS DRAM......................................................................................................... 62 12.6 BYTE ORDERING ON THE EXTENSION BUS ..................................................................................... 63 13. HIGH SPEED DATA INTERFACE (HSDI) ................................................................................ 65 13.1 IEEE 1394 INTERFACE .................................................................................................................. 66 13.1.1 The ‘AV7110 reads data from the MPEG2Lynx ................................................................... 67 |
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