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TMS320AV7110 Datasheet(PDF) 5 Page - Texas Instruments

Part No. TMS320AV7110
Description  Integrated Digital Set-top Box Decoder Functional Specification
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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TMS320AV7110 Datasheet(HTML) 5 Page - Texas Instruments

 
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DSP
TMS320AV7110
Revision 3.1
10/08/99 22:18
Page 5
List of Tables
TABLE 1. THE ‘AV7110 PINS.......................................................................................................................... 8
TABLE 2. SDRAM SELECTION REQUIREMENTS............................................................................................. 19
TABLE 3. DECODED BITSTREAM INFORMATION............................................................................................. 21
TABLE 4. ERROR STATISTICS AND MONITOR INFORMATION .......................................................................... 22
TABLE 5. FLAGS AND COMMANDS................................................................................................................. 22
TABLE 6. GPDMA SOURCES AND DESTINATIONS ........................................................................................ 23
TABLE 7. TRANSPORT PACKET INPUT INTERFACE PIN DESCRIPTION .............................................................. 27
TABLE 8. SUPPORTED VIDEO RESOLUTIONS FOR AUTOMATIC UP-SAMPLING ............................................... 34
TABLE 9. VIDEO DECODER COMMANDS ....................................................................................................... 35
TABLE 10. SCALING FACTORS FOR 4:3 MONITOR FOR PAL FORMAT. ........................................................... 37
TABLE 11. SCALING FACTORS FOR 16:9 MONITOR FOR PAL FORMAT. ......................................................... 37
TABLE 12. SCALING FACTORS FOR 4:3 MONITOR FOR NTSC FORMAT.......................................................... 37
TABLE 13. SCALING FACTORS FOR 16:9 MONITOR FOR NTSC FORMAT........................................................ 37
TABLE 14. THE ‘AV7110 MEMORY USAGE ................................................................................................. 38
TABLE 15. STORAGE OF B FRAMES............................................................................................................... 38
TABLE 16. TARGET OSD MEMORY SPACE IN SDRAM (IN BYTES).............................................................. 39
TABLE 17. SDRAM OSD WINDOW SIZE...................................................................................................... 42
TABLE 18. BLENDING LEVELS ...................................................................................................................... 44
TABLE 19. BLENDING AND TRANSPARENCY.................................................................................................. 44
TABLE 20. OSD MODULE OUTPUT CHANNEL CONTROL .............................................................................. 46
TABLE 21. SOURCE AND DESTINATION MEMORIES FOR BITBLT .................................................................. 47
TABLE 22. ALLOWABLE BITBLT WINDOW FORMATS .................................................................................. 47
TABLE 23. MULTIPLEXED VIDEO OUTPUT DEFINITIONS ............................................................................... 48
TABLE 24. DIGITAL OUTPUT CONTROL......................................................................................................... 51
TABLE 25. VARIS CODE SPECIFICATION...................................................................................................... 51
TABLE 26. THREE BYTE VARIS CODE......................................................................................................... 51
TABLE 27. CODING OF ASPECT RATIO IN THE VARIS CODE......................................................................... 51
TABLE 28. AUDIO MODULE REGISTERS ........................................................................................................ 52
TABLE 29. PCMCLK FREQUENCIES ............................................................................................................. 55
TABLE 30. SYSTEM TIME CLOCK MODEL....................................................................................................... 57
TABLE 31. EXTENSION BUS CHIP SELECT ASSIGNMENTS .............................................................................. 61
TABLE 32. HIGH SPEED DATA INTERFACE SIGNAL PIN ASSIGNMENT .......................................................... 65
TABLE 33. TYPES OF DMA TRANSFERS ALLOWED FOR DATA PORTS ......................................................... 65
TABLE 34. 1394 INTERFACE SIGNALS........................................................................................................... 67
TABLE 35. 1394 CONTROL LINES DESCRIPTION ........................................................................................... 67
TABLE 36. EXTERNAL DMA INTERFACE SIGNALS........................................................................................ 70
TABLE 37. EDMA REGISTER DEFINITION..................................................................................................... 71
TABLE 38. IEEE 1284 INTERFACE SIGNALS ................................................................................................. 73
TABLE 39. SMART CARD PIN DESCRIPTION.................................................................................................. 75
TABLE 40. GROUP 1 F VALUES ................................................................................................................... 76
TABLE 41. GROUP 2 F VALUES ................................................................................................................... 76
TABLE 42. TIMER CONTROL AND STATUS REGISTERS .................................................................................. 77
TABLE 43. I/O CONTROL/STATUS REGISTERS, IOCSRN............................................................................... 81
TABLE 44. GPIO_IRQ BIT DEFINITIONS ...................................................................................................... 81


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