A42MX09-2TQ100A datasheet(74/173 Pages) MICROSEMI

Part #	A42MX09-2TQ100A

Description	40MX and 42MX FPGA

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Manufacturer	MICROSEMI [Microsemi Corporation]

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74 / 173 page

40MX and 42MX FPGAs

DS2316 Datasheet Revision 16.0

66

CMOS Output Module Timing5

tDLH

Data-to-Pad HIGH

3.2

3.6

4.0

4.7

6.6

ns

tDHL

Data-to-Pad LOW

2.5

2.7

3.1

3.6

5.1

ns

tENZH

Enable Pad Z to HIGH

2.7

3.0

3.4

4.0

5.6

ns

tENZL

Enable Pad Z to LOW

3.0

3.3

3.8

4.4

6.2

ns

tENHZ

Enable Pad HIGH to Z

5.4

6.0

6.8

8.0

11.2

ns

tENLZ

Enable Pad LOW to Z

5.0

5.6

6.3

7.4

10.4 ns

tGLH

G-to-Pad HIGH

5.1

5.6

6.4

7.5

10.5 ns

tGHL

G-to-Pad LOW

5.1

5.6

6.4

7.5

10.5 ns

tLCO

I/O Latch Clock-to-Out

(Pad-to-Pad), 64 Clock Loading

5.7

6.3

7.1

8.4

11.9

ns

tACO

Array Clock-to-Out

(Pad-to-Pad), 64 Clock Loading

8.0

8.9

10.1

11.9

16.7 ns

dTLH

Capacitive Loading, LOW to

HIGH

0.03

0.04

0.06 ns/pF

1.

For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is

appropriate.

2.

Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

3.

Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules

can be obtained from the Timer utility.

4.

Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External

setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD

signal to the G input subtracts (adds) to the internal setup (hold) time.

5.

Delays based on 35 pF loading

Table 41 •

A42MX16 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)

Parameter / Description

–3 Speed

–2 Speed

–1 Speed

Std Speed –F Speed

Units

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

Logic Module Propagation Delays1

tPD1

Single Module

1.9

2.1

2.4

2.8

4.0

ns

tCO

Sequential Clock-to-Q

2.0

2.2

2.5

3.0

4.2

ns

tGO

Latch G-to-Q

1.9

2.1

2.4

2.8

4.0

ns

tRS

Flip-Flop (Latch) Reset-to-Q

2.2

2.4

2.8

3.3

4.6

ns

Logic Module Predicted Routing Delays2

tRD1

FO = 1 Routing Delay

1.1

1.2

1.4

1.6

2.3

ns

tRD2

FO = 2 Routing Delay

1.5

1.6

1.8

2.1

3.0

ns

tRD3

FO = 3 Routing Delay

1.8

2.0

2.3

2.7

3.8

ns

tRD4

FO = 4 Routing Delay

2.2

2.4

2.7

3.2

4.5

ns

tRD8

FO = 8 Routing Delay

3.6

4.0

4.5

5.3

7.5

ns

Table 40 •

A42MX16 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) (continued)

Parameter / Description

–3 Speed

–2 Speed

–1 Speed

Std Speed

–F Speed

Units

Min. Max. Min. Max.

Min. Max. Min. Max. Min. Max.

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