A42MX09-2TQ100A datasheet(61/173 Pages) MICROSEMI

Part #	A42MX09-2TQ100A

Description	40MX and 42MX FPGA

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Manufacturer	MICROSEMI [Microsemi Corporation]

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40MX and 42MX FPGAs

DS2316 Datasheet Revision 16.0

53

Input Module Predicted Routing Delays1

tIRD1

FO = 1 Routing Delay

2.9

3.3

3.8

4.5

6.3

ns

tIRD2

FO = 2 Routing Delay

3.6

4.2

4.8

5.6

7.8

ns

tIRD3

FO = 3 Routing Delay

4.4

5.0

5.7

6.7

9.4

ns

tIRD4

FO = 4 Routing Delay

5.1

5.9

6.7

7.8

11.0

ns

tIRD8

FO = 8 Routing

Delay

8.0

9.3

10.5

12.4

17.2

ns

Global Clock Network

tCKH

Input LOW to HIGH

FO = 16

FO = 128

6.4

7.4

8.4

9.9

13.8

ns

tCKL

Input HIGH to LOW

FO = 16

FO = 128

6.8

7.8

8.9

10.4

14.6

ns

tPWH

Minimum Pulse

Width HIGH

FO = 16

FO = 128

3.1

3.3

3.6

3.8

4.1

4.3

4.8

5.1

6.7

7.1

ns

tPWL

Minimum Pulse

Width LOW

FO = 16

FO = 128

3.1

3.3

3.6

3.8

4.1

4.3

4.8

5.1

6.7

7.1

ns

tCKSW

Maximum Skew

FO = 16

FO = 128

0.6

0.8

0.6

0.9

0.7

1.0

0.8

1.2

1.6

ns

tP

Minimum Period

FO = 16

FO = 128

6.5

6.8

7.5

7.8

8.5

8.9

10.1

10.4

14.1

14.6

ns

fMAX

Maximum

Frequency

FO = 16

FO = 128

113

109

105

101

96

92

83

80

50

48

MHz

TTL Output Module Timing4

tDLH

Data-to-Pad HIGH

4.7

5.4

6.1

7.2

10.0

ns

tDHL

Data-to-Pad LOW

5.6

6.4

7.3

8.6

12.0

ns

tENZH

Enable Pad Z to HIGH

5.2

6.0

6.9

8.1

11.3

ns

tENZL

Enable Pad Z to LOW

6.6

7.6

8.6

10.1

14.1

ns

tENHZ

Enable Pad HIGH to Z

11.1

12.8

14.5

17.1

23.9

ns

tENLZ

Enable Pad LOW to Z

8.2

9.5

10.7

12.6

17.7

ns

dTLH

Delta LOW to HIGH

0.03

0.04

0.06

ns/pF

dTHL

Delta HIGH to LOW

0.04

0.05

0.06

0.08

ns/pF

Table 37 •

A40MX04 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C) (continued)

Parameter / Description

–3 Speed

–2 Speed

–1 Speed

Std Speed –F Speed

Units

Min. Max. Min. Max. Min.

Max.

Min. Max. Min. Max.

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A42MX09-2TQ100A Datasheet(PDF) 61 Page - Microsemi Corporation

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