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PCM16C02 Datasheet(PDF) 5 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. PCM16C02
Description  Configurable Multiple Function PC Card Interface Chip
Download  42 Pages
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
Logo NSC - National Semiconductor (TI)

PCM16C02 Datasheet(HTML) 5 Page - National Semiconductor (TI)

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30 Pinout Description (Continued)
TABLE 3-2 Serial EEPROM Interface Pins
Pin
Pin
Pin
Level
Internal
Description
Name
Type
No
Compatibility
Resistor
EEDIEEDO
IO
81
TTL 6 mA
Serial Data in fromout to EEPROM
EECS
O
83
CMOS 6 mA
EEPROM Chip Select
EESK
O
82
CMOS 6 mA
EEPROM Clock Freq e MCLK(0)32
Note
The Enable EEPROM function is performed in software by writing to the EEPROM Control Register The Enable EEPROM bit will default to low (disabled)
upon power on
TABLE 3-3 Card-Side Interface Pins
Pin
Pin
Pin
Level
Internal
Description
Name
Type
No
Compatibility
Resistor
LDATA(150)
IO
1 – 5 7 – 13
TTL 6 mA
Hold Circuit
Card-side Data Bus
97 – 100
(Note 1)
SPK
IN
I
86
TTL Schmitt
Input Audio Signal
RI
IN(0)
I (Note 2)
23
TTL Schmitt
Ring Indicator for function 0
RI
IN(1)
I
87
TTL Schmitt
Ring Indicator for function 1
CIORD
O
19
CMOS 6 mA
IO read signals are passed through from HIORD
according to the expression shown below when a
valid address is decoded
CIORD
e
HIORD
a
REG
a
(CE1
CE2 )
CIOWR
O
18
CMOS 6 mA
IO write signals are passed through from HIOWR
according to the expression shown below when a
valid address is decoded
CIOWR
e
HIOWR
a
REG
a
(CE1
CE2 )
CWAIT(10)
I (Note 2)
96 31
TTL
Card-side transaction wait state inputs
CS(10)
O
95 30
CMOS 6 mA
Chip select for each function
BHE
O
17
CMOS 6 mA
Byte high enable When de-asserted and CS( )
asserted an 8-bit access on LDATA(70) is in
progress This holds for both odd and even
addresses When asserted and CS( )
asserted a
16-bit access on LDATA(150) is in progress
READY(10)
I
92 27
TTL
l
100k to VCC
Indicates that the function is either READY or
E
READY (ie - Busy) This signal is used to assert
the RdyBsy
bit in Pin Replacement Registers
CINT(10)
I (Note 2)
94 29
TTL Schmitt
Card-side interrupt input signals
SRESET(10)
O
93 28
CMOS 6 mA
Signals reset to Card-side functions
IOCS16(10)
I (Note 2)
91 26
TTL
This pin is asserted during an access to a function if
that function is capable of a 16-bit access
PCNTL(10)
O
15 14
CMOS 6 mA
Power management control signals or general
outputs
MCLK(10)
I
90 24
TTL Schmitt
Input clocks for function 0 and function 1
FCLK(10)
O
89 25
CMOS 6 mA
Output clock signals for function 0 and function 1
These may be gated onoff or be a divided value of
MCLK(10)
MEMWEH
O Tri
21
CMOS 6 mA
l
10k to VCC
Common Memory write output for upper byte of data
word
MEMWEL
O Tri
22
CMOS 6 mA
l
10k to VCC
Common Memory write output for lower byte of data
word
Note 1
The Hold Circuit will hold the signal to the logic value it was last set to when the line is TRI-STATE
This will insure that inputs do not float during a
TRI-STATE condition
Note 2
The CWAIT(0) CINT(0) RI
IN(0) and IOCS16(0)
pins are outputs (O) when function 0 is configured for the NAND Flash (NM29N16) Mode
5


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