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IDT72V8981 Datasheet(PDF) 1 Page - Integrated Device Technology

Part No. IDT72V8981
Description  3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V8981 Datasheet(HTML) 1 Page - Integrated Device Technology

 
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1
AUGUST 2003
3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
128 x 128
IDT72V8981
2003 Integrated Device Technology, Inc.
All rights reserved.
Product specifications subject to change without notice.
DSC-5702/4
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUSis a trademark of Mitel Corp.
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
••••• 128 x 128 channel non-blocking switch
••••• Serial Telecom Bus Compatible (ST-BUS®)
••••• 4 RX inputs—32 channels at 64 Kbit/s per serial line
••••• 4 TX output—32 channels at 64 Kbit/s per serial line
••••• Three-state serial outputs
••••• Microprocessor Interface (8-bit data bus)
••••• 3.3V Power Supply
••••• Available in 44-pin Plastic Leaded Chip Carrier (PLCC), and
44-pin Plastic Quad Flatpack (PQFP)
••••• Operating Temperature Range -40
°°°°°C to +85°°°°°C
••••• 3.3V I/O with 5V Tolerant Inputs
DESCRIPTION:
The IDT72V8981 is a ST-BUS® compatible digital switch controlled by a
microprocessor. The IDT72V8981 can handle as many as 128, 64 Kbit/s input
and output channels. Those 128 channels are divided into 4 serial inputs and
outputs, each of which consists of 32 channels (64 Kbit/s per channel) to form
a multiplexed 2.048 Mb/s stream.
FUNCTIONAL DESCRIPTION
AfunctionalblockdiagramoftheIDT72V8981deviceisshownbelow. The
serial streams operate continuously at 2.048 Mb/s and are arranged in 125
µs
wide frames each containing 32, 8-bit channels. Four input (RX0-3) and four
output (TX0-3)serialstreamsareprovidedintheIDT72V8981deviceallowing
a complete 128 x 128 channel non-blocking switch matrix to be constructed.
The serial interface clock (
C4i) for the device is 4.096 MHz.
The received serial data is internally converted to a parallel format by the
on chip serial-to-parallel converters and stored sequentially in a 128-position
DataMemory.Byusinganinternalcounterthatisresetbytheinput8KHzframe
pulse,
F0i, the incoming serial data streams can be framed and sequentially
addressed.
Data to be output on the serial streams may come from two sources: Data
Memory or Connection Memory. The Connection Memory is 16 bits wide and
Microprocessor Interface
Control Register
Timing
Unit
RX0
RX1
RX2
RX3
TX0
TX1
TX2
TX3
ODE
F0i
C4i
VCC
CS
DS
R/
W A0/
A5
GND
DTA D0/
D7
5702 drw01
Data
Memory
Output MUX
Connection
Memory
Receive
Serial Data
Streams
Transmit
Serial Data
Streams


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