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IDT72V8981 Datasheet(PDF) 5 Page - Integrated Device Technology

Part No. IDT72V8981
Description  3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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5
Commercial Temperature Range
IDT72V8981 3.3V Time Slot Interchange
Digital Switch 128 x 128
INITIALIZATION OF THE IDT72V8981
On initialization or power up, the contents of the Connection Memory High
can be in any state. This is a potentially hazardous condition when multiple TX
outputs are tied together to form matrices. The ODE pin should be held low on
power up to keep all outputs in the high impedance condition until the contents
of the CMH are programmed.
TABLE 1 — INPUT STREAM TO OUT-
PUT STREAM COMBINATIONS THAT
CAN
PROVIDE
THE
MINIMUM
2-CHANNEL DELAY
TABLE 2 — ADDRESS MAPPING
Connection Memory High
Channel 0
Channel 1
Channel 2
Channel 31
Channel 0
Channel 1
Channel 2
Channel 31
Channel 0
Channel 1
Channel 2
Channel 31
Channel 0
Channel 1
10000
1
10001
0
11111
1
Data Memory
0
0
0
0
1
1
1
0
2
1
1
3
0
1
1
0
1
1
10000
0
Channel 2
Channel 31
Connection Memory Low
Stream
Control Register
CRb7
External Address Bits
A5-A0
5702 drw07
The Control Register is only accessed when A5=0.
All other address bits have no effect when A5=0.
When A5 =1, only 32 bytes are randomly accessable
via A0-A4 at any one instant. Which 32 bytes are
accessed is determined by the state of CRb0 -CRb4.
The 32 bytes correlate to 32 channel of one ST-BUS
stream.
CRb6CRb5CRb4CRb3CRb2CRb1CRb0
CRb1CRb0
CRb4CRb3
Figure 3. Address Mapping
NOTES:
1. Writing to the Control Register is the only fast transaction.
2. Memory and stream are specified by the contents of the Control Register.
A5 A4 A3 A2 A1 A0
HEX ADDRESS
LOCATION
0
X
X
X
0
0
00-1F
Control Register(1)
100000
20
Channel 0(2)
100001
21
Channel 1(2)
1
•••••
1
•••••
1
•••••
111111
3F
Channel 31(2)
Input
Output Stream
0
1,2,3
13
Duringthemicroprocessorinitializationroutine,themicroprocessorshould
programthedesiredactivepathsthroughthematrices,andputallotherchannels
into the high impedance state. Care should be taken that no two connected TX
outputsdrivethebussimultaneously. WiththeCMHsetup,themicroprocessor
controlling the matrices can bring the ODE signal high to relinquish high
impedance state control to the Connection Memory High bits outputs.




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