SN65LVDM320

SLLS462 – AUGUST 2001

HIGH-SPEED DIFFERENTIAL 8-BIT REGISTERED TRANSCEIVER

1

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FEATURES

Full Parallel Access

– Buffer Mode: Up to 475 Megatransfers

– Flip-Flop Mode: Up to 300 Megatransfers

– Latch Mode: Up to 300 Megatransfers

Typical Output Voltage of 350 mV Across a

50-

Ω Load

– Pulse Skew Less Than 100 ps

– Output Skew Less Than 320 ps

– Part-to-Part Skew Less Than 1 ns

Assures a Low-Level Output

Power-Up/Down Glitch-Free Performance and

Hot Plugging

APPLICATIONS

logic diagram

DQ

CQ

DQ

CQ

LPBK

NODE

D

Q

C

Q

D

Q

C

Q

One-of-Eight Channels

OEB

OMODE1

OMODE2

CLK/LEAB

DA

IMODE1

IMODE2

CLK/LEBA

RA

OEA

LPBK

ENR

BY

BZ

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Copyright

 2001, Texas Instruments Incorporated

†Parallel data transfer through all channels simultaneously as defined by TIA/EIA–644 with tr of tf less than 30%of the unit interval.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.