IC42S8200 datasheet(31/76 Pages) ICSI

Part #	IC42S8200

Description	1Meg x 8 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

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Manufacturer	ICSI [Integrated Circuit Solution Inc]

Direct Link	http://www.icsi.com.tw

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1+" 5&

Integrated Circuit Solution Inc.

31

DR018-0A 07/10/2001

CAS latency = 2, 3, burst length = 4

Write Cycle Interruption Using the

Precharge Command

A write cycle can be interrupted by the execution of the

precharge command before that cycle completes. The

delay time (tWDL) from the precharge command to the point

where burst input is invalid, i.e., the point where input data

is no longer written to device internal memory is zero clock

cycles regardless of the CAS.

To inhibit invalid write, the DQM signal must be asserted

HIGH with the precharge command.

This precharge command and burst write command must

be of the same bank, otherwise it is not precharge interrupt

but only another bank precharge of dual bank operation.

PRE 0

WRITE A0

COMMAND

DQM

I/O

CLK

DIN A0

DIN A1

DIN A2

DIN A3

tWDL=0

WRITE (CA=A, BANK 0)

PRECHARGE (BANK 0)

MASKED BY DQM

PRE 0

WRITE A0

COMMAND

I/O

CLK

DIN A0

DIN A1

DIN A2

DIN A3

tDPL

WRITE (CA=A, BANK 0)

PRECHARGE (BANK 0)

CAS

CAS Latency

3

2

tWDL

00

tDPL

11

Inversely, to write all the burst data to the device, the

precharge command must be executed after the write data

recovery period (tDPL) has elapsed. Therefore, the

precharge command must be executed on one clock cycle

that follows the input of the last burst data item.

CAS latency = 2, 3, burst length = 4

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