later The designer must be careful however not to violate

the minimum RAS low time of the DRAMs He must also

guarantee that the minimum RAS precharge time is not vio-

lated during a transition from mode 1 to mode 5 when an

access is desired immediately following a refresh

If the processor tries to access memory while the DP8429 is

in mode 1 WAIT states should be inserted into the proces-

sor cycles until the DP8429 is back in mode 5 and the de-

sired access has been accomplished (see

Figure 9 )

Instead of using WAIT states to delay accesses when re-

freshing HOLD states could be used as follows RFRQ

could be connected to a HOLD or Bus Request input to the

system When convenient the system acknowledges the

HOLD or Bus Request by pulling M2 low

Using this

scheme HOLD will end as the RAS lines go low (RFIO

goes high) Thus there must be sufficient delay from the

time HOLD goes high to the DP8429 returning to mode 5 so

that the RAS low time of the DRAMs isn’t violated as de-

scribed earlier (see

Figure 3 for mode 1 refresh with Hold

states)

To perform a forced refresh the system will be inactive for

about four periods of RGCK For a frequency of 10 MHz

this is 400 ns To refresh 128 rows every 2 ms an average of

about one refresh per 16 ms is required With a RFCK period

of 16 ms and RGCK period of 100 ns DRAM accesses are

delayed due to refresh only 25% of the time If using the

Hidden Refresh available in mode 5 (refreshing with RFCK

high) this percentage will be even lower

MODE 4 - EXTERNALLY CONTROLLED ACCESS

In this mode all control signal outputs can be controlled

directly by the corresponding control input The enabled

RAS output follows RASIN CAS follows CASIN (with RC

low) WE follows WIN and RC determines whether the row

or the column inputs are enabled to the address outputs

(see

Figure 4 )

With RC high the row address latch contents are enabled

onto the address bus RAS going low strobes the row ad-

dress into the DRAMs After waiting to allow for sufficient

go low to enable the column address latch contents onto

the address bus When the column address is valid CAS

going low will strobe it into the DRAMs WIN determines

whether the cycle is a read write or read-modify-write ac-

cess Refer to

Figures 5a and 5b for typical Read and Write

timing using mode 4

Page or Nibble mode may be performed by toggling CASIN

once the initial access has been completed In the case of

page mode the column address must be changed before

Resistors required depends on DRAM load

DRAMs Maybe 16k 64k 256k 1M

For 4 Banks can drive 16 data bits

a

6 Check Bits for ECC

For 2 Banks can drive 32 data bits

a

7 Check Bits for ECC

For 1 Bank can drive 64 data bits

a

8 Check Bits for ECC

TLF8649 – 16

FIGURE 4 Typical Application of DP8429 Using External Control Access and Refresh in Modes 0 and 4

10