CY2SSTV16859
Document #: 38-07463 Rev. *B
Page 2 of 8
Pin Configuration (continued)
56 QFN Package
1
2
3
4
5
6
7
8
9
10
11
12
13
Q7A
Q5A
Q6A
Q4A
Q3A
Q2A
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
14
Q8B
27
26
25
24
23
22
21
20
19
18
17
16
15
28
42
41
40
39
38
37
36
35
34
33
32
31
30
D10
D8
D9
D7
RESET#
GND
CLK#
CLK
VDDQ
VDD
VREF
D6
D5
29
D4
44
45
46
47
48
49
50
51
52
53
54
55
56
43
Pin Description
Pin
Name
Description
TSSOP
QFN
51
38
RESET#
Disable Clocking and Reset Latch
7,15,34,39,43,50,54,58,63
37,48
GND
Ground
37,46,60
26,33,45
VDD
Supply Voltage
6,18,27,33,38,47,59,64
9,17,23,27,34,44,49,55
VDDQ
Supply Voltage, Quiet
45
32
VREF
Reference Voltage for Data Inputs
D(1:13)
16,14,13,12,11,10,9,8,5,4,3,2,1
7,6,5,4,3,2,1,56,54,53,52,51,50
QA(1:13)
Data Outputs
32,31,30,29,28,25,24,23,22,21,20,
19,17
22,21,20,19,18,16,15,14,13,12
11,10,8
QB(1:13)
Data Outputs
35,36,40,41,42,44,52,53,55,56,57,
61,62
24,25,28,29,30,31,39,40,41,42
43,46,47
D(1:13)
Data Inputs
48,49
35,36
CLK, CLK# Differential Clock Signals
Table 1. Function Table[1,2,3]
INPUTS
OUTPUT
RESET#
CLK
CLK#
D
Q
H
↑↓
LL
H
↑↓
HH
H
L or H
L or H
X
Q0
L
X or floating
X or floating
X or floating
L
Notes:
1.
H = High voltage level.
2.
L = Low voltage level.
3.
X = Don’t care.
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