LDTA114EET1G datasheet(12/12 Pages) LEIDITECH | Bias Resistor Transistors PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network

Part No.	LDTA114EET1G

Description	Bias Resistor Transistors PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network

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Manufacturer	LEIDITECH [Shanghai Leiditech Electronic Technology Co., Ltd]

Direct Link	http://www.leiditech.com

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12 / 12 page

G

M

0.08 (0.003)

X

D 3 PL

J

-X-

-Y-

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETERS

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD

FINISH THICKNESS. MINIMUM LEAD THICKNESS

IS THE MINIMUM THICKNESS OF BASE

MATERIAL.

4. 463C-01 OBSOLETE, NEW STANDARD 463C-02.

A

B

Y

12

3

N

2 PL

K

C

-T-

SEATING

PLANE

DIM

A

MIN

NOM

MIN

NOM

INCHES

1.50

1.60

1.70

0.059

MILLIMETERS

B

0.75

0.85

0.95

0.030

C

0.60

0.70

0.80

0.024

D

0.23

0.28

0.33

0.009

G

0.50 BSC

H

0.53 REF

J

0.10

0.15

0.20

0.004

K

0.30

0.40

0.50

0.012

L

1.10 REF

M

−−−

10

−−−

N

−−−

10

−−−

S

1.50

1.60

1.70

0.059

0.063

0.067

0.034

0.040

0.028

0.031

0.011

0.013

0.020 BSC

0.021 REF

0.006

0.008

0.016

0.020

0.043 REF

−−−

10

−−−

10

0.063

0.067

MAX

_

M

H

L

G

RECOMMENDED PATTERN

OF SOLDER PADS

S

SC-89

LDTA114EET1G Series

Shanghai Leiditech Electronic Co.,Ltd

Email: sale1@leiditech.com

Tel : +86- 021 50828806

Fax : +86- 021 50477059

Rev :

www.leiditech.com

01.06.2015

12/12

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LDTA114EET1G Datasheet(PDF) 12 Page - Shanghai Leiditech Electronic Technology Co., Ltd

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