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P80CL51HFHB Datasheet(PDF) 9 Page - NXP Semiconductors |
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P80CL51HFHB Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 40 page  Philips Semiconductors Product specification 80CL31/80CL51 Low-voltage single-chip 8-bit microcontrollers January 1995 9 2 OSCILLATOR PERIODS STRONG PULL UP +5V I/O PIN P3 P2 P1 n FROM PORT LATCH Q INPUT DATA READ PORT PIN INPUT BUFFER (a) STRONG PULL UP +5V P1 n I/O PIN FROM PORT LATCH Q (b) +5V I/O PIN EXT. PULL UP n INPUT BUFFER INPUT DATA FROM PORT LATCH Q READ PORT PIN (c) Figure 3. Ports The definition of port options for port 0 is slightly different. Two cases have to be examined. First, accesses to external memory (EA=0 or access above the built -in memory boundary), second, I/O accesses. External Memory Accesses Option 1: True 0 and 1 are written as address to the external memory (strong pull up is used). Option 2: An external pull up resistor is needed for external accesses. Option 3: Not allowed for external memory access as the port can only be used as output. I/O Accesses Option 1: When writing a 1 to the port-latch, the strong pull up p1 will be on for 2 oscillator periods. No weak pull up exists. Without an external pull up, this option can be used as a high-impedance input. Option 2: Open drain; quasi-bidirectional I/O with n-channel open drain output. Use as an output requires the connection of an external pull up resistor (see Figure 3(c)). Option 3: Push-Pull; output with drive capability in both polarities. Under this option, pins can only be used as outputs. Individual mask selection of the post-reset state is available on any of the above pins. Make your selection by appending “S” or “R” to option 1, 2, or 3 above (e.g. 1 S for a standard I/O to be set after RESET or 2R for an open-drain I/O to be reset after RESET). 1.3 Timer/event counter The 80CL51 contains two 16-bit Timer/Counter registers, Timer 0 and Timer 1, which can perform the following functions: – Measure time intervals and pulse durations – Count events – Generate interrupts requests |
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