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P80CL51HFH Datasheet(PDF) 4 Page - NXP Semiconductors |
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P80CL51HFH Datasheet(HTML) 4 Page - NXP Semiconductors |
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4 / 40 page  Philips Semiconductors Product specification 80CL31/80CL51 Low-voltage single-chip 8-bit microcontrollers January 1995 4 PIN DESCRIPTIONS PIN DESIGNATION FUNCTION QFP DIP DESIGNATION FUNCTION 40 1 P1.O/INT2 Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pullups. Port 1 pins that have 1s written to them are pulled HIGH by the internal pullups and in that state can be used as inputs The Port 1 41 2 P1.1/lNT3 to them are pulled HIGH by the internal pullups, and in that state can be used as inputs. The Port 1 output buffer can sink/source 4 LS TTL loads As inputs Port 1 pins that are externally pulled LOW 42 3 P1.2/lNT4 output buffer can sink/source 4 LS TTL loads. As inputs, Port 1 pins that are externally pulled LOW will source current (IlL in the characteristics) due to the internal pullups Port 1 also serves the 43 4 P1.3/INT5 will source current (IlL in the characteristics) due to the internal pullups. Port 1 also serves the alternative functions INT2 to INT9 44 5 P1.4/lNT6 alternative functions INT2 to INT9. 1 6 P1.5/lNT7 2 7 P1.6/lNT8 3 8 P1.7/lNT9 4 9 RST Reset: A high level on this pin for two machine cycles while the oscillator is running resets the device. 5–13 10-17 Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source 4 LS TTL inputs. Port 3 pins that have 1s written to them are pulled HIGH by the internal pull ups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally pulled LOW will source current (IlL in the characteristics) due to the internal pull ups. 5 10 P3.0/RXD/data RXD/data: Serial port receiver data input (asynchronous)or data input/output (synchronous) 7 11 P3.1/TXD/clock TXD/clock: Serial port transmitter data output (asynchronous) or clock output (synchronous) 8 12 P3.2/lNT0 INT0: External interrupt 0. 9 13 P3.3/lNT1 INT1: External interrupt 1. 10 14 P3.4/T0 T0: Timer 0 external input. 11 15 P3.5/T1 T1: Timer 1 external input. 12 16 P3.6/WR WR: External data memory write strobe. 13 17 P3.7/RD RD: External data memory read strobe. 14 18 XTAL2 Crystal output: Output of the inverting amplifier of the oscillator. Left open when external clock is used. Crystal input: Input to the inverting amplifier of the oscillator; also the input for an externally gen- erated clock source. 15 19 XTAL1 Crystal input: Input to the inverting amplifier of the oscillator; also the input for an externally generated clock source. 16 20 Vss Ground: Circuit ground potential. 18-25 21-28 P2.0-P2.7 Port 2: Port 2 is an 8-bit bidirectional 1/0 port with internal pullups. Port 2 pins that have 1s written to them are pulled HIGH by the internal pullups, and in that state can be used as inputs. The Port 2 output buffer can sink/source 4 LS TTL loads. Port 2 emits the high-order address byte during accesses to external memory that use 1 6-bit ad- dresses (MOVX @DPTR). In this application it uses the strong internal pullups when emitting 1s. During accesses to external memory that use 8-bit addresses (MOVX @Ri), Port 2 emits the con- tents of the P2 Special Function Register. 26 29 PSEN Program store enable output: Read strobe to external program memory. When executing code out of external program memory, PSEN is activated twice each machine cycle. However, during each access to external data memory two PSEN activations are skipped. 27 30 ALE Address Latch Enable: Output pulse for latching the low byte of the address during access to external memory. ALE is emitted at a constant rate of 1/6 of the oscillator frequency, and may be used for external timing or clocking purposes. 29 31 EA External Access: When EA is held High the CPU executes out of internal program memory (un- less the program counter exceeds 0FFFH). Holding EA LOW forces the CPU to execute out of external memory regardless of the value of the program counter. 30-37 32-39 P0.0-P00.7 Port 0: Port 0 is an 8-bit open drain bidirectional I/O port. As an open drain output port it can sink 8 LS TTL loads. Port 0 pins that have 1s written to them float, and in that state will function as high impedance inputs. Port 0 is also the multiplexed low order address and data bus during access to external memory. In this application it uses strong internal pull-ups when emitting logic 1s. 38 40 VDD Power supply. |
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