Electronic Components Datasheet Search |
|
XWM8195CFT Datasheet(PDF) 11 Page - Wolfson Microelectronics plc |
|
XWM8195CFT Datasheet(HTML) 11 Page - Wolfson Microelectronics plc |
11 / 31 page Advanced Information WM8195 w AI Rev 2.0 September 2002 11 DEVICE DESCRIPTION INTRODUCTION A block diagram of the device showing the signal path is presented on Page 1. The WM8195 samples up to three inputs (RINP, GINP and BINP) simultaneously. The device then processes the sampled video signal with respect to the video reset level or an internally/externally generated reference level using either one or three processing channels. Each processing channel consists of an Input Sampling block with optional Reset Level Clamping (RLC) and Correlated Double Sampling (CDS), a 8-bit programmable offset DAC and an 8-bit Programmable Gain Amplifier (PGA). The ADC then converts each resulting analogue signal to a 14-bit digital word. The digital output from the ADC is presented on a 14-bit wide bus, with optional 8+6-bit, 7+7-bit or 4+4+4+2-bit multiplexed formats. On-chip control registers determine the configuration of the device, including the offsets and gains applied to each channel. These registers are programmable via a serial or parallel interface. INPUT SAMPLING The WM8195 can sample and process one to three inputs through one or three processing channels as follows: Colour Pixel-by-Pixel: The three inputs (RINP, GINP and BINP) are simultaneously sampled for each pixel and a separate channel processes each input. The signals are then multiplexed into the ADC, which converts all three inputs within the pixel period. Monochrome: A single chosen input (RINP, GINP, or BINP) is sampled, processed by the corresponding channel, and converted by the ADC. The choice of input and channel can be changed via the control interface, e.g. on a line-by-line basis if required. Colour Line-by-Line: A single chosen input (RINP, GINP, or BINP) is sampled and multiplexed into the red channel for processing before being converted by the ADC. The input selected can be switched in turn (RINP → GINP → BINP → RINP…) together with the PGA and offset DAC control registers by pulsing the RLC/ACYC pin. This is known as auto-cycling. Alternatively, other sampling sequences can be generated via the control registers. This mode causes the blue and green channels to be powered down. Refer to the Line-by-Line Operation section for more details. RESET LEVEL CLAMPING (RLC) To ensure that the signal applied to the WM8195 lies within its input range (0V to AVDD) the CCD output signal is usually level shifted by coupling through a capacitor, CIN. The RLC circuit clamps the WM8195 side of this capacitor to a suitable voltage during the CCD reset period. A typical input configuration is shown in Figure 7 A clamp pulse, CL, is generated from MCLK and VSMP by the Timing Control Block. When CL is active the voltage on the WM8195 side of CIN,at RINP, is forced to the VRLC/VBIAS voltage (VVRLC) by switch 1. When the CL pulse turns off, the voltage at RINP initially remains at VVRLC but any subsequent variation in sensor voltage (from reset to video level) will couple through CIN to RINP. RLC is compatible with both CDS and non-CDS operating modes, as selected by switch 2. Refer to the CDS/Non-CDS Processing section. |
Similar Part No. - XWM8195CFT |
|
Similar Description - XWM8195CFT |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |