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5962-87539 Datasheet(PDF) 6 Page - ATMEL Corporation

Part # 5962-87539
Description  High Speed UV Erasable Programmable Logic Device
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

5962-87539 Datasheet(HTML) 6 Page - ATMEL Corporation

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Pin Capacitance
(f = 1 MHz, T = 25°C)
(1)
Typ
Max
Units
Conditions
CIN
58
pF
VIN = 0 V
COUT
68
pF
VOUT = 0 V
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power Up Reset
The registers in the AT22V10B are designed to reset during
power up. At a point delayed slightly from VCC crossing 3.8 V,
all registers will be reset to the low state. The output state will
depend on the polarity of the output buffer.
This feature is critical for state machine initialization. However,
due to the asynchronous nature of reset and the uncertainty of
how VCC actually rises in the system, the following conditions
are required:
1) The VCC rise must be monotonic,
2) After reset occurs, all input and feedback setup times must be
met before driving the clock pin high, and
3) The clock must remain stable during tPR.
Parameter
Description
Min
Typ
Max
Units
tPR
Power-Up
Reset Time
600
1000
ns
CLOCK
3.8 V
POWER
REGISTERED
OUTPUTS
tS
tPR
tW
Erasure Characteristics
The entire fuse array of an AT22V10B is erased after exposure
to ultraviolet light at a wavelength of 2537 Å. Complete erasure
is assured after a minimum of 20 minutes exposure using 12,000
µW/cm
2 intensity lamps spaced one inch away from the chip.
Minimum erase time for lamps at other intensity ratings can be
calculated from the minimum integrated erasure dose of 15
Wsec/cm
2. To prevent unintentional erasure, an opaque label
is recommended to cover the clear window on any UV erasable
PLD which will be subjected to continuous fluorescent indoor
lighting or sunlight.
Preload of Registered Outputs
The registers in the AT22V10B are provided with circuitry to
allow loading of each register asynchronously with either a high
or a low. This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A VIH level
on the I/O pin will force the register high; a VIL will force it low,
independent of the polarity bit (C0) setting. The preload state is
entered by placing an 10.5-V to 12-V signal on pin 8 on DIPs,
and pin 10 on SMPs. When the clock pin is pulsed high, the data
on the I/O pins is placed into the ten registers.
CLOCK
VH
OUTPUTS
DISABLED
PRELOAD
CLOCKED IN
PRELOAD DATA
PRELOAD
REGISTERED
VOLTAGE
REMOVED
tD
tD
tD
tD
tD
OUTPUT
FORCE I/O’S
TO VIH ORVIL
PRELOAD ENA.
OUTPUTS DIS.
tDMIN = 100 ns
Level forced on
registered output pin
during preload cycle
Register state
after cycle
VIH
High
VIL
Low
1-114
AT22V10B


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