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TMS470R1B1M Datasheet(PDF) 42 Page - Texas Instruments |
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TMS470R1B1M Datasheet(HTML) 42 Page - Texas Instruments |
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42 / 57 page  www.ti.com SPIn Master Mode External Timing Parameters Data Valid SPInSOMI SPInSIMO SPInCLK (clock polarity = 1) SPInCLK (clock polarity = 0) Master In Data Must Be Valid Master Out Data Is Valid 1 2 3 4 5 6 7 TMS470R1B1M 16/32-Bit RISC Flash Microcontroller SPNS109 – SEPTEMBER 2005 (CLOCK PHASE = 1, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input)(1)(2)(3) (see Figure 14) NO. MIN MAX UNIT 1 tc(SPC)M Cycle time, SPInCLK(4) 100 256tc(ICLK) tw(SPCH)M Pulse duration, SPInCLK high (clock polarity = 0) 0.5tc(SPC)M - tr 0.5tc(SPC)M + 5 2(5) tw(SPCL)M Pulse duration, SPInCLK low (clock polarity = 1) 0.5tc(SPC)M - tf 0.5tc(SPC)M + 5 tw(SPCL)M Pulse duration, SPInCLK low (clock polarity = 0) 0.5tc(SPC)M - tf 0.5tc(SPC)M + 5 3(5) tw(SPCH)M Pulse duration, SPInCLK high (clock polarity = 1) 0.5tc(SPC)M - tr 0.5tc(SPC)M + 5 tv(SIMO-SPCH)M Valid time, SPInCLK high after SPInSIMO data valid (clock polarity = 0) 0.5tc(SPC)M - 10 4(5) tv(SIMO-SPCL)M Valid time, SPInCLK low after SPInSIMO data valid (clock polarity = 1) 0.5tc(SPC)M - 10 ns tv(SPCH-SIMO)M Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 0) 0.5tc(SPC)M - 5 - tr 5(5) tv(SPCL-SIMO)M Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 1) 0.5tc(SPC)M - 5 - tf tsu(SOMI-SPCH)M Setup time, SPInSOMI before SPInCLK high (clock polarity = 0) 6 6(5) tsu(SOMI-SPCL)M Setup time, SPInSOMI before SPInCLK low (clock polarity = 1) 6 tv(SPCH-SOMI)M Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 0) 4 7(5) tv(SPCL-SOMI)M Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 1) 4 (1) The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set. (2) tc(ICLK) = interface clock cycle time = 1 / f(ICLK) (3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table. (4) When the SPI is in master mode, the following must be true: For PS values from 1 to 255: t c(SPC)M≥ (PS +1)tc(ICLK)≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits. For PS values of 0: tc(SPC)M = 2t c(ICLK)≥ 100 ns. (5) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1). Figure 14. SPIn Master Mode External Timing (CLOCK PHASE = 1) 42 |
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