1
Selection Guide
7C1001-12
7C1002-12
7C1001-15
7C1002-15
7C1001-20
7C1002-20
7C1001-25
7C1002-25
Maximum Access Time (ns)
12
15
20
25
Maximum Operating Current
Commercial
165
155
140
130
Military
165
150
140
Maximum Standby Current (mA)
Commercial
50
40
30
30
Military
40
30
30
PRELIMINARY
256K x 4 Static RAM
with Separate I/O
CY7C1001
CY7C1002
Logic Block Diagram
Pin Configuration
Features
D
High speed
tAA = 12 ns
D
Transparent write (7C1001)
D
CMOS for optimum speed/power
D
Low active power
910 mW
D
Low standby power
275 mW
D
2.0V data retention (optional)
100 µW
D
Automatic powerdown when
deselected
D
TTL compatible inputs and outputs
Functional Description
The CY7C1001 and CY7C1002 are high
performance CMOS static RAMs orga
nized as 262,144 x 4 bits with separate I/O.
Easy memory expansion is provided by ac
tive LOW chip enable (CE) and three
state drivers. Both devices have an auto
matic powerdown feature, reducing the
power consumption by more than 65%
when deselected.
Writing to the device is accomplished by
taking both chip enable (CE) and write en
able (WE) inputs LOW. Data on the four
input pins (I0throughI3)iswrittenintothe
memory location specified on the address
pins (A0 through A17).
Reading the device is accomplished by tak
ing chip enable (CE) LOW while write en
able (WE) remains HIGH. Under these
conditions, the contents of the memory lo
cation specified ontheaddresspinswillap
pear on the four data output pins (O0
through O3).
The data output pins on the CY7C1001
and the CY7C1002 are placed in a high
impedance state when the device is dese
lected (CE HIGH). The CY7C1002's out
puts are also placed in a highimpedance
state duringawriteoperation(CEandWE
LOW). In a write operation on the
CY7C1001, the output pins will carry the
same data as the inputs after a specified
delay.
The CY7C1001 and CY7C1002 are avail
able in standard 300milwide DIPs and
SOJs.
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
Top View
DIP/SOJ
12
13
29
32
31
30
16
15
17
18
7C1001
C1001-1
NC
A16
A17
A0
A1
A2
A10
A11
A12
A13
A14
A9
I3
I2
VCC
A15
A3
A4
A5
A6
A7
A8
NC
I0
I1
O1
O0
O2
CE
GND
O3
WE
7C1002
512 x 512 x 4
ARRAY
COLUMN
DECODER
POWER
DOWN
INPUT BUFFER
I0
7C1002 ONLY
7C1001 ONLY
A0
C1001-2
I1
I2
I3
O0
O1
O2
O3
CE
WE
A1
A2
A3
A4
A5
A6
A7
A8
Cypress Semiconductor Corporation
D
3901 North First Street
D San Jose D
CA 95134
D 408-943-2600
November 1991 - Revised April 1995
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