PRELIMINARY
CY7C1366C
CY7C1367C
Document #: 38-05542 Rev. *A
Page 11 of 27
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells pri-
or to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required - that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
TAP AC Switching Characteristics Over the operating Range[3, 4]
Parameter
Symbol
Min
Max
Unit
Clock
TCK Clock Cycle Time
tTCYC
50
ns
TCK Clock Frequency
tTF
20
MHz
TCK Clock HIGH time
tTH
25
ns
TCK Clock LOW time
tTL
25
ns
Output Times
TCK Clock LOW to TDO Valid
tTDOV
5ns
TCK Clock LOW to TDO Invalid
tTDOX
0ns
Setup Times
TMS Set-Up to TCK Clock Rise
tTMSS
5ns
TDI Set-Up to TCK Clock Rise
tTDIS
5ns
Capture Set-Up to TCK Rise
tCS
5
Hold Times
TMS hold after TCK Clock Rise
tTMSH
5ns
TDI Hold after Clock Rise
tTDIH
5ns
Capture Hold after Clock Rise
tCH
5ns
t
TL
Test Clock
(TCK)
123456
Test Mode Select
(TMS)
tTH
Test Data-Out
(TDO)
tCYC
Test Data-In
(TDI)
tTMSH
tTMSS
tTDIH
tTDIS
tTDOX
tTDOV
DON’T CARE
UNDEFINED